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docs(hhtl): PR-X4 pre-sprint prompt — 4×4 splat cascade (W4-W5)#166

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May 19, 2026
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docs(hhtl): PR-X4 pre-sprint prompt — 4×4 splat cascade (W4-W5)#166
AdaWorldAPI merged 1 commit into
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claude/pr-x4-splat-cascade-pre-sprint-prompt

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Summary

Drafts the W4-W5 splat-cascade sprint pre-sprint prompt in the same shape as the GridLake (ade8edb2) and PR-X14′ (56b26716) prompts. Captures the (4×4)×(4×4)×(4×4)×(4×4) tier scheme as the load-bearing structural identity between Gaussian splatting and the cognitive shader — verbatim from pr-x4-design.md:57-72:

L4 (16384²)  framebuffer / experience memory   ←  4×4 super-grid of L3
L3 (4096²)   scene aggregation                  ←  16×16 super-grid of L2
L2 (256²)    regional resonance                  ←  4×4 super-grid of L1
L1 (64²)     per-cell context                    ←  4×4 covariance footprint per splat

Area-uniform 16× branching, L4/L1 area ratio = 16⁴ = 65,536 matching the cell-count ratio 16384²/64² exactly. Per-dim branching is non-uniform (4 / 16 / 4) — the L2→L3 transition has a wider gather to span the scene-aggregation scale.

What's in the prompt

  • Why this exists — the splat ≡ cognitive substrate identity table verbatim from pr-x4-design.md:36-48
  • The 4×4 tier scheme — load-bearing verbatim claim with area-uniform 16× branching rationale
  • Mechanical shapeTileInstance { tier, block_row, block_col, gaussian_id, confidence } on BlockedGrid<SplatBinList, 1, 1>, and splat4d::cascade::CascadeAddr(u16) with 4-nibble level encoding
  • The four splat gaps PR-X4 owns: G1 deg-3 SH inquiry-direction, G2 INT4×32 packed dot, G3 NARS truth-revision kernel, G4 fast_exp_x16 precision audit. G5 CTU-mode encoder belongs to PR-X9, not PR-X4.
  • P0-4 carry-over from PR-X10 A12b — hilbert3d_encode([15,15,15], 4) = 2925, expected 4095 is the gate for the A2 (CascadeAddr) worker. PR-X4 cannot ship L4 cascade addressing until A12b's L4 fix lands.
  • Worker DAG: A1 (chain dep) → A2 [gated], A3, A4, A5 parallel
  • Done criteria — refactor complete, cascade addressing (incl. L4 round-trip exhaustive), four splat gaps with parity tests, tier-cascade composition (L5 moment-match + L6 Pillar-8 sandwich), composition swap behind splat4d-nars-compose feature flag, no regressions on the 2370-test green union
  • Five forbidden constraints:
    1. No bespoke Hilbert-3D in PR-X4 — consume linalg::hilbert and wait for A12b fix
    2. No crate::simd::* extension from inside PR-X4 (route through vertical-simd-consumer-contract.md)
    3. No write to lance-graph upstream (PR-X4 lives in ndarray, consumes contract via bridge)
    4. No 4×4 tier-stride departure (would break the splat ≡ cognitive identity)
    5. No NARS-revision activation by default (feature-gated until W7 closure swap)

Schedule slot

W4-W5, 5 workers, no new Q-marker — slot is fixed in hhtl-substrate-execution-prompt.md. Spawn depends on:

  • ✅ PR-X10 A6 (linalg::distance, by W2)
  • ⚠️ PR-X10 A8 (linalg::sh deg 4-7, by W2)
  • ⚠️ PR-X10 A12b (linalg::hilbert L4 fix) — GATE
  • ✅ PR-X1 + PR-X2 (GridLake) — by W2.5 (α) or W3 (β) per Q-NEW-2
  • ✅ PR-X14′ (contract) — by W2.5/W3 per Q-NEW-2
  • ✅ PR-X11 (jc consolidation Spd3 ops) — by W3

If GridLake + X14′ slip past W3 (e.g., Cell A-β), PR-X4 starts late by the same margin. No schedule extension owed by PR-X4 itself.

Carry-overs back into other sprints

  • PR-X10 A12b: must ship round_trip_level4_exhaustive test + NEXT_STATE re-derivation before PR-X4 A2 spawns (gate)
  • PR-X11: Spd3 ops (sandwich, sqrt, from_rows) are deps for PR-X4 L5/L6
  • PR-X9 (W6-W7): consumes PR-X4's CascadeAddr to skip-encode unchanged basins — PR-X4 must ship the address surface by end-W5
  • PR-X7 (post-Phase-2): consumes PR-X4's SplatCell<D> as typed-cell-signature bridge — keep API forward-compatible
  • W7 closure swap: flips splat4d-nars-compose from off to on after G4 audit verdict

Test plan

Docs-only PR (1 new file, 438 lines, additive).

  • Verify the prompt reads cleanly on the GitHub web view
  • Confirm verbatim citations match the current pr-x4-design.md and pp13-brutally-honest-tester-verdict.md on master 13dfcf9d
  • Cross-reference set complete (11 docs cited)
  • Hand off to PR-X4 sprint coordinator at W4 spawn (after Q-NEW-1/Q-NEW-2 cell decided in docs(hhtl): plan-review savant preflight brief for Q-NEW-1 + Q-NEW-2 #165)

Companion to the open substrate-pair work

Cross-references

  • .claude/knowledge/pr-x4-design.md — master design (merged PR docs(hhtl): Phase 2 entry — consolidation refinements + canary inhabitance + substrate execution prompt #162)
  • .claude/knowledge/pr-x10-linalg-core-design.mdlinalg::sh/hilbert/distance deps
  • .claude/knowledge/pp13-brutally-honest-tester-verdict.md § P0-4 — the L4 Hilbert-3D bug
  • .claude/knowledge/pr-arithmetic-inventory.md § L4-L8 — splat gap taxonomy
  • .claude/knowledge/hhtl-gridlake-pre-sprint-prompt.md + hhtl-pr-x14-substrate-contract-prompt.md — substrate prompts PR-X4 consumes

Generated by Claude Code

Companion to GridLake (ade8edb) and PR-X14′ (56b2671) prompts, in the
same shape. Captures the W4-W5 splat-cascade sprint that promotes
splat3d from "bespoke 16×16 tile binner" to "typed multi-resolution
cognitive evolution operator" with the (4×4)×(4×4)×(4×4)×(4×4) tier
scheme as the load-bearing structural identity between Gaussian
splatting and the cognitive shader.

Verbatim citations:
- pr-x4-design.md:36-48 (graphics ≡ cognitive substrate identity table)
- pr-x4-design.md:57-72 (the tier scheme, area-uniform 16× branching,
  non-isotropic 4/16/4 per-dim branching rationale)
- pr-x4-design.md:108-118 (TileInstance v2 shape)
- pp13-brutally-honest-tester-verdict.md:32-37 (the P0-4 L4 Hilbert-3D
  bug — hilbert3d_encode([15,15,15], 4) = 2925, expected 4095)

Worker DAG: A1 TileInstance + BlockedGrid refactor (chain dep) →
A2 CascadeAddr [GATED on A12b L4 fix], A3 deg-3 SH inquiry-direction,
A4 INT4×32 packed dot (3 backends + parity), A5 NARS truth-revision
kernel + fast_exp_x16 precision audit.

Five forbidden constraints:
  1. No bespoke Hilbert-3D in PR-X4 — consume linalg::hilbert
  2. No crate::simd::* extension from inside PR-X4
  3. No write to lance-graph upstream
  4. No 4×4 tier-stride departure
  5. No NARS-revision activation by default (feature-gated)

Carry-overs back into other sprints:
- PR-X10 A12b L4 fix is a gate for A2 spawn
- PR-X11 Spd3 ops are deps for L5/L6
- PR-X9 (W6-W7) consumes CascadeAddr; PR-X4 must ship by end-W5
- W7 closure swap activates the splat4d-nars-compose feature

No new Q-marker; W4-W5 slot is fixed. PR-X4 starts late only if
GridLake + X14′ slip past W3 (per Q-NEW-1/Q-NEW-2 cell choice).
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pub struct CascadeAddr(u16); // 4 nibbles, one per tier level

impl CascadeAddr {
pub fn level(&self, l: u8) -> u8 { (self.0 >> (l * 4) & 0xF) as u8 }
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P2 Badge Fix nibble indexing in CascadeAddr::level example

The prompt defines tiers as 1 = L1 ... 4 = L4 but the sample accessor uses self.0 >> (l * 4), which makes level(1) read the second nibble and level(4) shift a u16 by 16 bits (overflow panic in debug builds). If implementers copy this API literally, L1/L4 addressing will be wrong or crash when validating level-4 paths; use validated 0-based indexing or compute with (l - 1) * 4 for 1-based tiers.

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@AdaWorldAPI AdaWorldAPI merged commit c7b3f38 into master May 19, 2026
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