simd: SimdProfile fine-grained detection + cpu-* pinning + leaf 7,1 CPUID

[AdaWorldAPI]

Summary

Four orthogonal additions that complement (don't duplicate) the simd_runtime/ + CpuOps work shipped in PRs #185–#187. The parallel session built the runtime-dispatch trampolines and the GCC-codename DTO lookup; this PR adds the fine-grained CPUID detection + silicon-identity enum + compile-time pinning half of the matrix-doc plan.

Layer	Where it lives now
Per-op LazyLock<fn> trampolines (vnni_dot_u8_i8, add_mul_f32, casts, matmul)	crate::simd_runtime::* (PR #185)
Codename-to-tier DTO lookup (cpu_ops_for_cpu("sapphirerapids"))	crate::simd_runtime::cpu_ops (PR #187)
Silicon-identity enum + runtime CPUID detect ladder	crate::hpc::simd_profile::* (this PR)
Compile-time profile pinning via cargo features	cpu-* features (this PR)

SimdProfile::detect() is strictly more granular than CpuOps-tier selection — it discriminates GraniteRapids vs SapphireRapids (amx_fp16 bit), CooperLake vs IceLakeSp (BF16 / VBMI mutex), TigerLakeU vs IceLakeSp (VP2INTERSECT). The two pieces compose cleanly; simd_profile() could feed CpuOps selection in a future commit if you want, but neither subsumes the other today.

Commits

de52a446 fix(simd):  SimdProfile::detect() consults amx_available() — Risk #3 closure
03b30e54 feat(examples): simd_profile_probe — hardware verification binary
b9a6fa0e feat(simd):  cpu-* cargo features for compile-time SimdProfile pinning
db3669e8 feat(simd):  SimdProfile enum + detect() implements dispatch matrix

What each commit adds

db3669e8 — SimdProfile enum + detect()

crate::hpc::simd_profile::SimdProfile — 14-variant enum that names silicon generations directly:

pub enum SimdProfile {
    GraniteRapids, SapphireRapids,
    Zen4Avx512, CooperLake,
    TigerLakeU, IceLakeSp, CascadeLake, SkylakeX,
    ArrowLake, HaswellAvx2,
    A76DotProd, A72Fast, A53Baseline,
    Scalar,
}

detect() walks the decision tree from .claude/knowledge/td-simd-cpu-dispatch-matrix.md § "SimdProfile::detect() mapping" lines 271-305 verbatim. Four load-bearing invariants preserved:

1. GraniteRapids checked before SapphireRapids — GNR is a strict superset; checking SPR first would route GNR silicon as SPR and leave AMX-FP16 unused.
2. Zen4 vs SPR via amx_tile (both have F+VBMI+BF16+FP16).
3. CooperLake vs IceLakeSp via mutually-exclusive bits (CPL has BF16 without VBMI; ICX has VBMI without BF16).
4. TigerLakeU vs IceLakeSp via avx512vp2intersect.

Also adds 3 new SimdCaps fields: avx512fp16, avx512vp2intersect, amx_fp16 — plus the CPUID leaf 7,1 reader (gated on leaf 7,0 EAX max-subleaf ≥ 1). Master's simd_caps.rs currently has no leaf 7,1 read; GNR's AMX-FP16 lives at CPUID.07H.1H:EAX bit 21, so the fix is a prerequisite for GNR dispatch regardless of which detection ladder uses it.

LazyLock-cached simd_profile() accessor.

b9a6fa0e — cpu-* cargo features (compile-time pinning)

13 mutually-exclusive features that fold simd_profile() to a const at compile time and elide the LazyLock entirely:

cpu-gnr  cpu-spr  cpu-zen4  cpu-cpl  cpu-tigerlake  cpu-icx  cpu-clx  cpu-skx
cpu-arrowlake  cpu-haswell  cpu-a76  cpu-a72  cpu-a53

Mutual exclusion enforced by a const assert (_PIN_COUNT <= 1); enabling two simultaneously produces a build error. Pair with -Ctarget-cpu=<codename> for the codegen side. Use case: per-silicon distribution where --features cpu-spr produces an SPR-specialized binary that bypasses runtime detection.

Complementary to runtime-dispatch (PR #185): runtime-dispatch ships one binary that adapts across silicon; cpu-* ships per-silicon binaries that fold dispatch out entirely.

03b30e54 — examples/simd_profile_probe

Boot-on-silicon diagnostic per the matrix doc's TEST-promotion checklist § step 1: "Boot the binary on the silicon and confirm simd_profile() returns the expected variant." Prints:

• Resolved SimdProfile variant + arch/family flags
• Compile-time pinning status (with pinned variant if active)
• Every CPUID-derived SimdCaps bit
• ARM heuristic profile (when running aarch64)
• Active compile-time target features
• Per-variant matrix-doc cell summary
• Re-runs the pinning_consistency invariant so regressions in the cfg cascade are caught post-deploy

cargo run --example simd_profile_probe --release                 # runtime
cargo run --example simd_profile_probe --release --features cpu-spr   # pinned

de52a446 — Risk #3 closure (AMX OS-state gating)

SimdProfile::detect() now consults simd_amx::amx_available() (CPUID + OSXSAVE + XCR0[17,18] + arch_prctl(XCOMP_PERM, 18) on Linux 5.19+) and demotes when CPUID reports AMX but the OS/hypervisor hasn't enabled the tile XSAVE state.

Verified on this Sapphire Rapids build host: CPUID reports amx_tile=1, amx_bf16=1, but amx_available() returns false (hypervisor masks XCR0 bits 17/18 or the prctl request fails). Without the fix, detect() would resolve as SapphireRapids and dispatch tables would route to AMX kernels that SIGILL. With the fix, it demotes to Zen4Avx512 (AVX-512 BF16/FP16 path), matching what amx_available() consumers already do inline.

Probe surfaces the CPUID-vs-OS gap directly so the demotion is visible without reading source.

Diff vs current master (eb6444f)

 Cargo.toml                     |  30 +++
 examples/simd_profile_probe.rs | 202 ++++++++++++++
 src/hpc/mod.rs                 |   3 +
 src/hpc/simd_caps.rs           |  99 ++++++-
 src/hpc/simd_profile.rs        | 597 +++++++++++++++++++++++++++++++++++++++++
 src/simd.rs                    |  16 ++
 6 files changed, 943 insertions(+), 4 deletions(-)

Test plan

• 2106 lib tests pass on default config (was 2095 on master; +9 in simd_profile::tests, +2 in simd_caps::tests).
• 9 new simd_profile::tests:
  • detect_returns_a_valid_profile, determinism, arch_partitioning_is_consistent
  • x86_target_lands_inside_x86_family, aarch64_target_lands_inside_aarch64_family
  • has_avx512_is_subset_of_is_x86 (subset invariants on has_avx512() + has_amx())
  • names_are_stable_and_unique (O(n²) sweep)
  • pinning_default_is_off, pinning_consistency
• 2 new simd_caps::tests: fp16_fields_consistent_on_non_x86, has_amx_fp16_requires_amx_tile (defense-in-depth: AMX-FP16 requires AMX-TILE in the convenience method).
• cargo clippy --lib -- -D warnings clean under default, --features cpu-spr, --features runtime-dispatch.
• cargo fmt --all --check clean.
• Mutex compile_error verified by attempting --features "cpu-spr,cpu-zen4" — fails as expected with the const-assert citation.
• Probe runs on this SPR host, resolves to Zen4Avx512 (Risk This PR ports high-performance computing (HPC) features from the rustynum library into ndarray, adding comprehensive linear algebra, statistical operations, hyperdimensional computing (HDC), and signal processing capabilities. The implementation uses a pluggable backend architecture with runtime CPU detection (AVX-512 → AVX2 → scalar) for optimal performance across different hardware. #3 demotion), pinning bit shows OFF; with --features cpu-zen4 shows ACTIVE pinning.

How it composes with PRs #185–#187

                ┌─ crate::simd_runtime::* (PR #185)  ←  runtime LazyLock trampolines
                │
caps = simd_caps()
                │
                ├─ crate::simd_runtime::cpu_ops (PR #187)  ←  named-target lookup
                │
                └─ crate::hpc::simd_profile::detect() (THIS PR)  ←  CPUID-based 14-variant detect
                                                                    + amx_available() OS-gate
                                                                    + cpu-* pinning constants

The matrix doc's TEST-promotion workflow needs the fine-grained variant (you can't promote "SPR" cells if your detector only says "amx_int8 tier"). SimdProfile is that surface; PR #187's CpuOps is the dispatch-table glue.

Out of scope (separate PRs)

• Wiring simd_profile() as the seed for CpuOps selection (would replace the current is_x86_feature_detected! inside cpu_ops()).
• Promoting matrix-doc cells DOC → TEST using the probe binary on real SPR/GNR/Zen4 silicon.
• A simd_profile().coarse() -> &'static str codename mapping for parity with cpu_ops_for_cpu().

https://claude.ai/code/session_01UwJuKqP828qyX1VkLgGJFS

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Guard cpu- pinning by target architecture*

The new pinning map accepts ARM pins on x86_64 (and x86 pins on aarch64) with no compile-time guard, so --features cpu-a76 on an x86_64 build will still compile and force simd_profile() to report A76DotProd. That makes is_x86()/is_aarch64() reflect the feature flag rather than the actual target and can silently route callers into the wrong dispatch family if a build matrix or release script passes the wrong cpu-* feature. Please add compile_error!/#[cfg] checks so incompatible pin features fail fast for the current target_arch.

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