Add ARM NEON SIMD support for Raspberry Pi (3/4/5)#89
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AdaWorldAPI merged 4 commits intomasterfrom Apr 12, 2026
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simd_caps.rs: - Add aarch64 fields: neon (baseline), asimd_dotprod, fp16, aes, sha2, crc32 - Runtime detection via is_aarch64_feature_detected!() (stable since Rust 1.61) - ArmProfile enum: A53Baseline (Pi Zero 2W/3), A72Fast (Pi 4/Orange Pi 4), A76DotProd (Pi 5/Orange Pi 5) with estimated tok/s and effective lanes - Convenience: has_neon(), has_dotprod(), has_fp16(), has_crypto(), arm_profile() simd_dispatch.rs: - Add NeonDotProd + Neon tiers (aarch64 detect with scalar fn ptr fallback) - Auto-vectorization via -C target-feature=+neon covers the scalar wrappers simd.rs: - LazyLock Tier enum: Neon + NeonDotProd variants for ARM - PREFERRED_*_LANES constants: aarch64-specific widths (4×f32, 2×f64, 8×i16) All 12 simd_caps + simd_dispatch tests pass on x86. NEON intrinsic wrappers remain in simd_neon.rs (scaffolded, not yet activated). https://claude.ai/code/session_017ZN5PNEf8boFBgorUZVrFU
simd_neon.rs: complete rewrite from scaffolding to working implementation. Tier 1 — Baseline NEON (ALL aarch64: Pi Zero 2W, Pi 3, Pi 4, Pi 5): - dot_f32x4_neon: 4×f32 dot product via vmulq + vpaddq - fma_f32x4_neon: vfmaq_f32 accumulate (codebook core) - hsum_f32x4: horizontal sum via pairwise add (no vaddvq needed) - popcount_u8x16: vcntq_u8 (native byte popcount, faster than x86!) - hamming_u8x16: XOR + popcount + widening sum (Fingerprint<256>) - base17_l1_neon: vabdq_s16 + vpaddlq (17×i16 L1 distance) - codebook_gather_f32x4_neon: N centroids → one vector via NEON add Tier 2 — A72 Fast (Pi 4, Orange Pi 4): - codebook_gather_f32x4_a72: 2× unrolled for dual-pipeline saturation Tier 3 — A76 DotProd + FP16 (Pi 5, Orange Pi 5): - dot_i8x16_neon: vdotq_s32 (4× throughput vs manual widen) - codebook_gather_i8_dotprod: quantized i8 centroids via SDOT - f16x4_to_f32x4: FCVTL via inline asm (stable Rust, no f16 type needed!) - f16x8_to_f32x8: dual FCVTL/FCVTL2 (Pi 5 dual-issue) - f32x4_to_f16x4: FCVTN via inline asm - f32x8_to_f16x8: FCVTN + FCVTN2 Scalar fallbacks: - f16_to_f32_scalar: IEEE 754 half-precision bit manipulation - f32_to_f16_scalar: truncation path - f16_to_f32_batch / f32_to_f16_batch: runtime fp16 detection + fallback 4 tests passing on x86 (scalar paths), NEON paths compile-gated. https://claude.ai/code/session_017ZN5PNEf8boFBgorUZVrFU
No existing code modified. New functions appended at end of file: Scalar (exact, all platforms): - f16_to_f32_ieee754: lossless widening (subnormals, Inf, NaN preserved) - f32_to_f16_ieee754_rne: narrowing with RNE (Round-to-Nearest-Even) Batch (runtime-detected, tiered): - f16_to_f32_batch_ieee754: AVX-512F (16-wide) → F16C (8-wide) → scalar - f32_to_f16_batch_ieee754_rne: AVX-512F (16-wide) → F16C (8-wide) → scalar Uses hardware F16C instructions (stable target_feature since Rust 1.68): VCVTPH2PS: u16 → f32 (exact) VCVTPS2PH: f32 → u16 (imm8=0x00 for RNE) IEEE 754 binary16: 1 sign + 5 exp (bias 15) + 10 mantissa Range: ±65504, precision: 3.31 decimal digits 6 new tests, all passing. Existing BF16 tests unaffected. https://claude.ai/code/session_017ZN5PNEf8boFBgorUZVrFU
…sion Adds clear table + warning at top of f16 block: - F16 (5-bit exp, 10-bit mant) ≠ BF16 (8-bit exp, 7-bit mant) - F16 is for sensors/audio/ARM interchange - BF16 pipeline (above) is for GGUF model weight calibration - Other sessions must NOT use f16_to_f32_ieee754 for GGUF hydration No code changes. Documentation only. https://claude.ai/code/session_017ZN5PNEf8boFBgorUZVrFU
This was referenced Apr 30, 2026
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Summary
Implement full ARM NEON SIMD support with tiered kernels for Raspberry Pi models (Zero 2W, Pi 3, Pi 4, Pi 5) and other aarch64 SBCs. Replaces scaffolding with production-ready code using stable Rust 1.94+ inline assembly and runtime feature detection.
Key Changes
Core NEON Implementation (
src/simd_neon.rs)Tier 1 (Baseline): NEON 128-bit kernels for all aarch64 CPUs
dot_f32x4_neon(): 4×f32 dot product via FMAhamming_u8x16(): Hamming distance with nativevcntq_u8popcountbase17_l1_neon(): L1 distance for 17-element vectorscodebook_gather_f32x4_neon(): Codebook accumulation kernelTier 2 (A72 Fast): Pi 4 / Orange Pi 4 LTS optimizations
codebook_gather_f32x4_a72(): 2× unroll to saturate dual NEON pipelinesTier 3 (A76 DotProd): Pi 5 / Orange Pi 5 advanced features
dot_i8x16_neon(): SDOT instruction for 4× int8 throughputcodebook_gather_i8_dotprod(): Quantized codebook via dotprodFP16 Support (ARMv8.2+, stable via inline asm):
f16x4_to_f32x4()/f16x8_to_f32x8(): FCVTL conversion (1 instruction per 4 elements)f32x4_to_f16x4()/f32x8_to_f16x8(): FCVTN conversionf16_to_f32_batch(),f32_to_f16_batch()SIMD Capability Detection (
src/hpc/simd_caps.rs)Extended
SimdCapsstruct with ARM fields:neon: Mandatory on aarch64 (always true)asimd_dotprod: ARMv8.2+ (Pi 5 only)fp16: ARMv8.2+ half-precisionaes,sha2,crc32: Crypto extensions (Pi 3+)New
ArmProfileenum for board identification:A53Baseline: Pi Zero 2W, Pi 3 (NEON only)A72Fast: Pi 4, Orange Pi 4 (NEON + crypto, 2× throughput)A76DotProd: Pi 5, Orange Pi 5 (NEON + dotprod + fp16)Convenience methods:
has_neon(),has_dotprod(),has_fp16(),has_crypto(),arm_profile()Dispatch Layer (
src/hpc/simd_dispatch.rs)SimdTier::NeonandSimdTier::NeonDotProdvariantsTier Selection (
src/simd.rs)is_aarch64_feature_detected!()(stable since Rust 1.61)F16 IEEE 754 Support (
src/simd_avx512.rs)https://claude.ai/code/session_017ZN5PNEf8boFBgorUZVrFU