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# ndarray — AdaWorldAPI HPC Expansion

A complete high-performance numerical computing stack built on top of the [rust-ndarray/ndarray](https://github.com/rust-ndarray/ndarray) foundation. This fork adds 55 HPC modules with 880 tests, covering BLAS L1-L3, LAPACK, FFT, vector math, quantized inference, and hardware-specific SIMD kernels spanning Intel AMX through Raspberry Pi NEON — all on **stable Rust 1.94**, zero nightly features.

The upstream ndarray provides excellent n-dimensional array abstractions. We keep all of that and add what it was never designed to do: compete with NumPy's OpenBLAS on GEMM, run codebook inference on a 5-watt Pi 4, and handle half-precision floats that Rust doesn't even have a stable type for yet.

[Deutsche Version / German Version](README-DE.md)

## Upstream vs. Fork — Feature by Feature

### ISA Coverage (Instruction Set Architecture)

| ISA / Feature | Upstream ndarray | **AdaWorldAPI Fork** | Speedup vs. Upstream |
|---------------|-----------------|---------------------|---------------------|
| **AVX-512** (512-bit, 16×f32) | Scalar fallback | Native `__m512` types, F32x16/F64x8/U8x64 | **~8×** |
| **AVX-512 VNNI** (int8 dot) | Scalar fallback | `vpdpbusd` 64 MACs/instr + dispatch | **~32×** |
| **AVX-512 BF16** (bfloat16) | Not available | Hardware `vcvtneps2bf16` + RNE emulation | **new** |
| **AVX-512 VPOPCNTDQ** (popcount) | Scalar fallback | Native 512-bit popcount for Hamming | **~16×** |
| **AMX** (Tile Matrix, 256 MACs) | Not available | Inline asm `.byte` encoding, stable Rust | **~128×** vs. scalar |
| **AVX2 + FMA** (256-bit, 8×f32) | Via matrixmultiply | Own Goto-GEMM 6×16 + dispatch table | **~4×** |
| **AVX2 F16C** (f16 hardware) | Not available | IEEE 754 f16, Double-f16, Kahan, Scaler | **new** |
| **AVX-VNNI** (ymm, 32 MACs) | Not available | Arrow Lake / NUC 14 support | **new** |
| **SSE2** (128-bit, 4×f32) | Via matrixmultiply | Scalar polyfill with same API | 1× (baseline) |
| **NEON** (128-bit, 4×f32) | Scalar fallback | 3-tier: A53/A72/A76 with pipeline awareness | **~4×** |
| **NEON dotprod** (ARMv8.2) | Not available | `vdotq_s32` for 4× int8 throughput (Pi 5) | **~16×** vs. scalar |
| **NEON fp16** (ARMv8.2) | Not available | `FCVTL`/`FCVTN` via inline asm | **new** |
| **NEON Popcount** | Not available | `vcntq_u8` native byte popcount | **faster than x86 SSE** |
| **WASM SIMD128** | Not available | Scaffolding prepared | in progress |

### BLAS / Numerics

| Operation | Upstream | **Fork** | Improvement |
|-----------|----------|----------|-------------|
| GEMM (1024²) | ~13 GFLOPS (cache cliff) | **139 GFLOPS** (Goto blocking) | **10.5×** |
| Dot Product | Via matrixmultiply | 4× unrolled + FMA | ~2× |
| BLAS L1 (axpy, scal, nrm2) | Not available | SIMD-accelerated, all tiers | **new** |
| BLAS L2 (gemv, ger, trsv) | Not available | SIMD-accelerated | **new** |
| LAPACK (LU, Cholesky, QR) | Not available | Pure-Rust implementation | **new** |
| FFT | Not available | Cooley-Tukey radix-2 | **new** |
| Activations (sigmoid, GELU) | Not available | SIMD F32x16 vectorization | **new** |
| Quantization (BF16, INT8) | Not available | VNNI + AMX + scalar fallback | **new** |

### Data Types

| Type | Upstream | **Fork** | Note |
|------|----------|----------|------|
| f32 | Standard | Standard + F32x16 SIMD | Same + SIMD acceleration |
| f64 | Standard | Standard + F64x8 SIMD | Same + SIMD acceleration |
| **f16** (IEEE 754) | **Not available** | u16 carrier + F16C/FCVTL hardware | Stable Rust, no nightly |
| **BF16** (bfloat16) | **Not available** | Hardware + RNE emulation (bit-exact) | GGUF calibration |
| i8/u8 (quantized) | Not available | VNNI dot, Hamming, popcount | INT8 inference |
| i16 (Base17) | Not available | L1 distance, SIMD widen/narrow | Codebook encoding |

### Dispatch and Detection

| Aspect | Upstream | **Fork** |
|--------|----------|----------|
| SIMD detection | None (delegates to BLAS) | `LazyLock<SimdCaps>` — detect once, forever |
| Dispatch cost | No own dispatch | **0.3ns** (fn pointer table, no branch) |
| ARM profiling | No ARM awareness | `ArmProfile`: A53/A72/A76 with tok/s estimate |
| big.LITTLE | Not handled | Correct feature intersection (RK3399/RK3588) |
| CPU detection | Per-call runtime | Once via LazyLock, then pointer deref only |
A complete high-performance numerical computing stack built on top of [rust-ndarray/ndarray](https://github.com/rust-ndarray/ndarray). 55 HPC modules, 880 tests, BLAS L1-L3, LAPACK, FFT, quantized inference, SIMD kernels from Intel AMX to Raspberry Pi NEON — **stable Rust 1.94**, zero nightly.

### What Upstream Does on Each Target

```
Upstream on x86_64: → matrixmultiply crate (external, AVX2 if available)
Upstream on aarch64: → Scalar (no NEON, no intrinsics)
Upstream on wasm: → Scalar
Upstream on riscv: → Scalar

Fork on x86_64: → AVX-512 F32x16 / AVX2 F32x8 / SSE2 / Scalar (tiered)
Fork on aarch64: → NEON A76+dotprod / NEON A72 2×pipe / NEON A53 / Scalar
Fork on wasm: → WASM SIMD128 (prepared) / Scalar
Fork on riscv: → Scalar (RISC-V V Extension prepared)
```

## Performance
[Deutsche Version](README-DE.md) | [Full Feature Comparison (146 modules)](COMPARISON.md)

### GEMM (General Matrix Multiply)
## Why This Exists

| Matrix Size | Upstream ndarray | **This Fork** | NumPy (OpenBLAS) | PyTorch CPU | GPU (RTX 3060) |
|-------------|-----------------|---------------|------------------|-------------|----------------|
| 512×512 | ~20 GFLOPS | **47 GFLOPS** | ~45 GFLOPS | ~40 GFLOPS | ~1,200 GFLOPS |
| 1024×1024 | ~13 GFLOPS | **139 GFLOPS** | ~120 GFLOPS | ~100 GFLOPS | ~3,500 GFLOPS |
| 2048×2048 | ~13 GFLOPS | **~150 GFLOPS** | ~140 GFLOPS | ~130 GFLOPS | ~5,000 GFLOPS |
| What | Us | GPU (RTX 3060) | GPU (H100) | NumPy CPU |
|------|-----|----------------|------------|-----------|
| **Cosine similarity** | **2,400M/s** (palette u8) | ~300M/s (IVF-PQ) | ~1,500M/s (cuVS) | ~50M/s (dot) |
| **GEMM 1024x1024** | **139 GFLOPS** | 3,500 GFLOPS | 30,000 GFLOPS | 120 GFLOPS |
| **Codebook inference** | **2,000 tok/s @ 5W** (Pi 4) | ~100K tok/s @ 170W | ~500K tok/s @ 700W | N/A |
| **Energy efficiency** | **37M ops/s/W** | 1.8M ops/s/W | 2.1M ops/s/W | 1.8M ops/s/W |
| **Startup latency** | **0 ms** (no kernel launch) | 2-10 ms | 2-10 ms | 50 ms (Python) |
| **Hardware cost** | **$0** (runs on any CPU) | $350 | $30,000 | $0 |
| **PCIe transfer** | **None** (data in L1 cache) | Required | Required | None |
| **Rust stable** | **Yes** (1.94) | CUDA toolkit | CUDA toolkit | Python |

Upstream hits a cache cliff at 1024×1024: no tiling, no threading, no microkernel. Our Goto implementation eliminates this entirely. At 1024×1024 we deliver **10.5× the throughput of upstream** and match NumPy's decades-old OpenBLAS within measurement noise.
GPU wins at large dense GEMM. We win at **everything else**: similarity search, latency-sensitive inference, edge deployment, energy efficiency, and cost. A $35 Raspberry Pi 4 at 5 watts outperforms a $350 GPU at 170 watts for codebook inference — because table lookups don't need floating-point hardware.

### Codebook Inference (Token Generation)
## Core Architecture

Not matrix multiplication — O(1) table lookup per token. No GPU required.
Five layers built on top of upstream ndarray's array primitives:

| Hardware | ISA | tok/s | 50-Token Latency | Power |
|----------|-----|-------|------------------|-------|
| Sapphire Rapids | AMX (256 MACs/instr) | **380,000** | 0.13 ms | 250W |
| Xeon / i9-13900K | AVX-512 VNNI (64 MACs) | **10,000–50,000** | 1–5 ms | 150W |
| i7-13800K + VNNI | AVX2-VNNI (32 MACs) | **3,000–10,000** | 5–17 ms | 65W |
| Raspberry Pi 5 | NEON + dotprod | **2,000–5,000** | 10–25 ms | 5W |
| Raspberry Pi 4 | NEON (dual pipeline) | **500–2,000** | 25–100 ms | 5W |
| Pi Zero 2W | NEON (single pipeline) | **50–500** | 100–1000 ms | 2W |
**SIMD Polyfill** (`simd.rs`, `simd_avx512.rs`, `simd_avx2.rs`, `simd_neon.rs`) — `std::simd`-compatible types (`F32x16`, `F64x8`, `U8x64`, `I32x16`) on stable Rust via `core::arch`. Detection once via `LazyLock<SimdCaps>`, dispatch via frozen function pointer table (0.3ns per call).

At 5 watts, a Pi 4 generates a 50-token voice assistant response in under 100 milliseconds.
**Backend** (`backend/`) — Pluggable BLAS: pure-Rust Goto-GEMM (default), Intel MKL (feature-gated), OpenBLAS (feature-gated). Native backend: 6x16 f32 + 6x8 f64 microkernels, cache-blocked L1/L2/L3, 16-thread split-borrow parallelism.

### Cosine Similarity via Palette Distance (Integer-Only)
**HPC Library** (`hpc/`, 146 files) — BLAS L1-L3, LAPACK, FFT, VML, statistics, activations, quantized ops. Every module SIMD-accelerated through the frozen dispatch table.

Traditional cosine requires floating-point: `dot(a,b) / (|a| × |b|)`. We replace this with a single u8 table lookup.
**Codec** (`fingerprint.rs`, `bgz17_bridge.rs`, `cam_pq.rs`, `palette_distance.rs`) — Encoding stack for compressed inference: Fingerprint<256>, Base17, CAM-PQ, palette semiring. O(1) per token — table lookups replace matrix multiplication.

| Precision Tier | Sigma Band | Max Cosine Error | Speed |
|----------------|------------|-----------------|-------|
| **Foveal** (1/40 σ) | Inner 2.5% | ±0.004 (0.4%) | **611M lookups/s** |
| **Good** (1/4 σ) | Inner 68% | ±0.02 (2%) | **611M lookups/s** |
| **Near** (1 σ) | Inner 95% | ±0.08 (8%) | **2.4B lookups/s** |
| F32 exact cosine | — | 0 | ~50M/s |
**Burn Integration** (`crates/burn/`) — SIMD-augmented burn-ndarray backend wiring `F32x16` into tensor ops and activations.

**611 million cosine-equivalent comparisons per second using only integer operations** — 12× faster than SIMD f32 dot product. The 256×256 table (64KB) fits entirely in L1 cache.
## Upstream vs. Fork

### Half-Precision Weight Transcoding
### ISA Coverage

Tested on 15M parameter model (Piper TTS scale):
| ISA | Upstream ndarray | **This Fork** | Speedup |
|-----|-----------------|---------------|---------|
| AVX-512 (16×f32) | Scalar fallback | Native `__m512` types | **~8×** |
| AVX-512 VNNI (int8) | Scalar fallback | 64 MACs/instr + dispatch | **~32×** |
| AVX-512 BF16 | Not available | Hardware + RNE emulation | **new** |
| AVX-512 VPOPCNTDQ | Scalar fallback | Native 512-bit popcount | **~16×** |
| AMX (256 MACs) | Not available | Inline asm, stable Rust | **~128×** |
| AVX2 + FMA (8×f32) | Via matrixmultiply | Goto-GEMM + dispatch | **~4×** |
| AVX2 F16C | Not available | IEEE 754 f16 + precision toolkit | **new** |
| NEON (4×f32) | Scalar fallback | 3-tier: A53/A72/A76 | **~4×** |
| NEON dotprod | Not available | `vdotq_s32` (Pi 5) | **~16×** |
| NEON fp16 | Not available | `FCVTL`/`FCVTN` via asm | **new** |

| Format | Size | Max Error | RMSE | Throughput |
|--------|------|-----------|------|------------|
| f32 (original) | 60 MB | — | — | — |
| **f16 (IEEE 754)** | **30 MB** | 7.3×10⁻⁶ | 2.5×10⁻⁶ | 94M params/s |
| **Scaled-f16** | **30 MB** | 4.9×10⁻⁶ | 2.1×10⁻⁶ | 91M params/s |
| **Double-f16** | 60 MB | 5.7×10⁻⁸ | 1.8×10⁻⁸ | 42M params/s |
### What Upstream Does on Each Target

## What We Build That Nobody Else Does
```
Upstream on x86_64: → matrixmultiply crate (AVX2 if available, no AVX-512)
Upstream on aarch64: → Scalar (no NEON, no intrinsics)
Upstream on wasm: → Scalar

### 1. Complete SIMD Polyfill on Stable Rust
Fork on x86_64: → AVX-512 / AVX2 / SSE2 / Scalar (tiered, auto-detected)
Fork on aarch64: → NEON A76+dotprod / A72 2×pipe / A53 / Scalar (tiered)
Fork on wasm: → WASM SIMD128 (prepared) / Scalar
```

`std::simd` has been nightly-only for years. We implement the same type surface using stable `core::arch` intrinsics. The dispatch is a `LazyLock<SimdCaps>` singleton: one CPUID call, frozen forever, zero per-call overhead.
## Performance

### 2. Half-Precision Types Without Nightly
### GEMM

Rust's `f16` type is nightly-only. We use `u16` as carrier + hardware instructions via stable `#[target_feature]` (F16C on x86, `FCVTL`/`FCVTN` via inline `asm!()` on ARM). IEEE 754 bit-exact at hardware speed.
| Matrix Size | Upstream | **This Fork** | NumPy | PyTorch CPU | GPU (RTX 3060) |
|-------------|---------|---------------|-------|-------------|----------------|
| 512×512 | ~20 GFLOPS | **47 GFLOPS** | ~45 | ~40 | ~1,200 |
| 1024×1024 | ~13 GFLOPS | **139 GFLOPS** | ~120 | ~100 | ~3,500 |
| 2048×2048 | ~13 GFLOPS | **~150 GFLOPS** | ~140 | ~130 | ~5,000 |

### 3. AMX on Stable Rust
**10.5× over upstream** at 1024×1024 — matches NumPy OpenBLAS.

Intel AMX intrinsics are nightly-only. We emit instructions via `asm!(".byte ...")` encoding — 256 MACs per instruction, verified on Rust 1.94 stable. Reduces distance table build from 24–48h to ~80 minutes.
### Codebook Inference

### 4. Tiered ARM NEON for Single-Board Computers
| Hardware | ISA | tok/s | 50-tok Latency | Power |
|----------|-----|-------|----------------|-------|
| Sapphire Rapids | AMX | **380,000** | 0.13 ms | 250W |
| Xeon | AVX-512 VNNI | **10K–50K** | 1–5 ms | 150W |
| **Pi 5** | **NEON+dotprod** | **2K–5K** | 10–25 ms | **5W** |
| **Pi 4** | **NEON dual** | **500–2K** | 25–100 ms | **5W** |

Three tiers with runtime detection: A53 Baseline (Pi Zero/3), A72 Fast (Pi 4, dual pipeline), A76 DotProd (Pi 5, `vdotq_s32` + native fp16). big.LITTLE aware.
### Cosine via Palette Distance

### 5. Frozen Dispatch (0.3ns per call)
| Tier | Error | Speed | vs. GPU (RTX 3060) |
|------|-------|-------|---------------------|
| **Foveal** (1/40σ) | 0.4% | **611M/s** | **~2× faster** |
| **Near** (1σ) | 8% | **2,400M/s** | **~8× faster** |
| F32 exact | 0% | 50M/s | 6× slower |
| RTX 3060 IVF-PQ | ~5% | ~300M/s | baseline |
| H100 cuVS | ~2% | ~1,500M/s | 5× our cost |

Function pointer table, not per-call branching. `LazyLock<SimdDispatch>` → one indirect call, no atomic, no branch prediction miss.
611M cosine-equivalent lookups/sec using only integer operations. The 256×256 table (64KB) lives in L1 cache — no FP division, no multiplication, no PCIe transfer.

### 6. BF16 RNE Bit-Exact with Hardware
### f16 Weight Transcoding

Pure AVX-512-F emulation of `VCVTNEPS2BF16`, verified bit-for-bit on 1M+ inputs including subnormals, Inf, NaN, and halfway ties.
| Format | Size | Max Error | Speed |
|--------|------|-----------|-------|
| f32 | 60 MB | — | — |
| **f16** | **30 MB** | 7.3e-6 | 94M/s |
| **Scaled-f16** | **30 MB** | 4.9e-6 | 91M/s |
| **Double-f16** | 60 MB | 5.7e-8 | 42M/s |

### 7. Cognitive Codec Stack
## What We Build That Nobody Else Does

Fingerprint<256>, Base17 VSA, CAM-PQ, Palette Semiring, bgz7/bgz17 — compressed model weights (201GB → 685MB) with O(1) inference.
1. **SIMD Polyfill on Stable** — `F32x16`/`F64x8`/`U8x64` via `core::arch`, not nightly `std::simd`
2. **f16 Without Nightly** — `u16` carrier + F16C hardware / ARM `FCVTL` via `asm!()`
3. **AMX on Stable** — `asm!(".byte ...")` encoding, 256 MACs/instruction
4. **Tiered ARM NEON** — A53/A72/A76 with pipeline + big.LITTLE awareness
5. **0.3ns Dispatch** — LazyLock frozen fn-pointer table, no per-call branching
6. **BF16 RNE Bit-Exact** — Pure AVX-512-F emulates `VCVTNEPS2BF16` bit-for-bit
7. **Cognitive Codec Stack** — Fingerprint → Base17 → CAM-PQ → Palette → bgz7 (201GB → 685MB, O(1) inference)

## Quick Start

Expand All @@ -163,28 +121,26 @@ use ndarray::Array2;
use ndarray::hpc::simd_caps::simd_caps;

let a = Array2::<f32>::ones((1024, 1024));
let b = Array2::<f32>::ones((1024, 1024));
let c = a.dot(&b); // AVX-512 / AVX2 / NEON — zero code changes
let c = a.dot(&a); // AVX-512 / AVX2 / NEON — auto

let caps = simd_caps();
if caps.avx512f { println!("AVX-512: 16 lanes"); }
if caps.neon { println!("ARM: {}", caps.arm_profile().name()); }
if caps.neon { println!("{}", caps.arm_profile().name()); }
```

```bash
cargo build --release
cargo build --release --target aarch64-unknown-linux-gnu # Pi 4
RUSTFLAGS="-C target-cpu=x86-64-v4" cargo build --release # AVX-512
cargo test # 880 HPC tests
cargo build --release # auto-detect
cargo build --release --target aarch64-unknown-linux-gnu # Pi 4
RUSTFLAGS="-C target-cpu=x86-64-v4" cargo build --release # AVX-512
cargo test # 880 tests
```

## Ecosystem

| Repository | Role | Uses ndarray for |
|------------|------|-----------------|
| [lance-graph](https://github.com/AdaWorldAPI/lance-graph) | Graph query + codec spine | Fingerprint, CAM-PQ, CLAM, BLAS, ZeckF64 |
| [home-automation-rs](https://github.com/AdaWorldAPI/home-automation-rs) | Smart home + voice AI | Codebook inference, VITS TTS, SIMD audio |
| Repo | Role |
|------|------|
| [lance-graph](https://github.com/AdaWorldAPI/lance-graph) | Graph query + codec spine |
| [home-automation-rs](https://github.com/AdaWorldAPI/home-automation-rs) | Smart home + voice AI |

## License

MIT OR Apache-2.0 (same as upstream ndarray)
MIT OR Apache-2.0
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