Embedded-Systems-Arch-Assignment1

The purpose of this assignment is to create a simple arithmetic logic unit using VHDL and to simulate it to examine its operation

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
CPU_PROJ		CPU_PROJ
README.md		README.md
comp_tb_output.png		comp_tb_output.png
comparator.vhd		comparator.vhd
comparator_tb.vhd		comparator_tb.vhd
shift.vhd		shift.vhd
shift_tb.vhd		shift_tb.vhd

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