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1. sparrow-cluster sparrow-cluster Public

   A four-core cache-coherent RISC-V multicore SoC built around Sparrow-V, implementing MSI coherence, private caches, and a shared-memory architecture.

   SystemVerilog

2. agentic-rtl-security agentic-rtl-security Public

   Agentic RTL security discovery benchmark comparing directed tests, random fuzzing, and LLM-guided MMIO trace generation on a seeded SystemVerilog mini-SoC.

   Python

3. tinyNPU tinyNPU Public

   An open-source INT8 neural processing unit IP for edge AI, supporting configurable matrix multiplication and reusable SoC integration.

   SystemVerilog 1

4. sparrow-ml sparrow-ml Public

   An end-to-end ML toolchain that converts trained neural networks into hardware-ready workloads for the Sparrow hardware ecosystem.

   Python

5. axi-router axi-router Public

   2x4 AXI4-Stream packet router in SystemVerilog with round-robin arbitration, packet-level locking, deterministic random verification, and an executable UVM environment.

   SystemVerilog

6. sparrow-v sparrow-v Public

   An open-source RV32I processor designed for edge AI research, featuring a custom vector extension for quantized and sparse machine learning workloads.

   SystemVerilog