GitHub - Ag22EE/Single-Core-processor: logic modules written in Verilog The modules/files in this repository are not to be used for academic purposes. Using or copying these files with the intent of submission for an assignment is against the Aggie Honor Code. Copying work can result in suspension or expulsion. "On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work." This is public repository, meaning if you were able to find it, so can school officials. If you are suspected of copying files from this repo then you can be subject to provide evidence that your submission was your own work. Texas A&M University students are responsible for authenticating all work submitted to an instructor. If asked, students must be able to produce proof that the item submitted is indeed the work of that student. Students must keep appropriate records at all times. The inability to authenticate one’s work, should the instructor request it, is sufficient grounds to initiate an academic dishonesty case.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
DataMemory.v		DataMemory.v
Honor Code Policy_ Read Before access.md		Honor Code Policy_ Read Before access.md
InstructionMemory.v		InstructionMemory.v
MiniRegisterFile.v		MiniRegisterFile.v
NextPClogic.v		NextPClogic.v
SignExtender.v		SignExtender.v
SingleCycleControl.v		SingleCycleControl.v
SingleCycleProc.v		SingleCycleProc.v
SingleCycleProcTest.v		SingleCycleProcTest.v

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logic modules written in Verilog The modules/files in this repository are not to be used for academic purposes. Using or copying these files with the intent of submission for an assignment is against the Aggie Honor Code. Copying work can result in suspension or expulsion. "On my honor, as an Aggie, I have neither given nor received unauthorized…