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[PWGEM/Dilepton] add possibility to apply TOF chi2 cut #8319

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Merged
dsekihat merged 1 commit into from
Nov 6, 2024
Merged

[PWGEM/Dilepton] add possibility to apply TOF chi2 cut #8319

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16 changes: 16 additions & 0 deletions PWGEM/Dilepton/Core/DielectronCut.cxx
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,9 @@
// Class for dilepton Cut
//

#include <utility>
#include <set>

#include "Framework/Logger.h"
#include "PWGEM/Dilepton/Core/DielectronCut.h"

Expand Down Expand Up @@ -112,6 +115,12 @@ void DielectronCut::SetMaxFracSharedClustersTPC(float max)
mMaxFracSharedClustersTPC = max;
LOG(info) << "Dielectron Cut, set max fraction of shared clusters in TPC: " << mMaxFracSharedClustersTPC;
}
void DielectronCut::SetRelDiffPin(float min, float max)
{
mMinRelDiffPin = min;
mMaxRelDiffPin = max;
LOG(info) << "Dielectron Cut, set rel. diff. between Pin and Ppv range: " << mMinRelDiffPin << " - " << mMaxRelDiffPin;
}
void DielectronCut::SetChi2PerClusterTPC(float min, float max)
{
mMinChi2PerClusterTPC = min;
Expand Down Expand Up @@ -139,6 +148,13 @@ void DielectronCut::SetMeanClusterSizeITS(float min, float max, float minP, floa
mMaxP_ITSClusterSize = maxP;
LOG(info) << "Dielectron Cut, set mean cluster size ITS range: " << mMinMeanClusterSizeITS << " - " << mMaxMeanClusterSizeITS;
}
void DielectronCut::SetChi2TOF(float min, float max)
{
mMinChi2TOF = min;
mMaxChi2TOF = max;
LOG(info) << "Dielectron Cut, set chi2 TOF range: " << mMinChi2TOF << " - " << mMaxChi2TOF;
}

void DielectronCut::SetTrackDca3DRange(float min, float max)
{
mMinDca3D = min;
Expand Down
22 changes: 14 additions & 8 deletions PWGEM/Dilepton/Core/DielectronCut.h
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Expand Up @@ -57,6 +57,7 @@ class DielectronCut : public TNamed
kTPCCrossedRows,
kTPCCrossedRowsOverNCls,
kTPCFracSharedClusters,
kRelDiffPin,
kTPCChi2NDF,
kTPCNsigmaEl,
kTPCNsigmaMu,
Expand Down Expand Up @@ -209,6 +210,9 @@ class DielectronCut : public TNamed
if (!IsSelectedTrack(track, DielectronCuts::kTPCFracSharedClusters)) {
return false;
}
if (!IsSelectedTrack(track, DielectronCuts::kRelDiffPin)) {
return false;
}
if (!IsSelectedTrack(track, DielectronCuts::kTPCChi2NDF)) {
return false;
}
Expand All @@ -217,11 +221,6 @@ class DielectronCut : public TNamed
return false;
}

// // TOF beta cut
// if (track.hasTOF() && (track.beta() < mMinTOFbeta || mMaxTOFbeta < track.beta())) {
// return false;
// }

// PID cuts
if constexpr (isML) {
if (!PassPIDML(track, collision)) {
Expand Down Expand Up @@ -282,7 +281,7 @@ class DielectronCut : public TNamed
{
bool is_el_included_TPC = mMinTPCNsigmaEl < track.tpcNSigmaEl() && track.tpcNSigmaEl() < mMaxTPCNsigmaEl;
bool is_pi_excluded_TPC = track.tpcInnerParam() < mMaxPinForPionRejectionTPC ? (track.tpcNSigmaPi() < mMinTPCNsigmaPi || mMaxTPCNsigmaPi < track.tpcNSigmaPi()) : true;
bool is_el_included_TOF = mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl;
bool is_el_included_TOF = (mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl) && (track.hasTOF() && track.tofChi2() < mMaxChi2TOF);
return is_el_included_TPC && is_pi_excluded_TPC && is_el_included_TOF;
}

Expand All @@ -294,7 +293,7 @@ class DielectronCut : public TNamed
bool is_pi_excluded_TPC = track.tpcInnerParam() < mMaxPinForPionRejectionTPC ? (track.tpcNSigmaPi() < mMinTPCNsigmaPi || mMaxTPCNsigmaPi < track.tpcNSigmaPi()) : true;
bool is_ka_excluded_TPC = track.tpcNSigmaKa() < mMinTPCNsigmaKa || mMaxTPCNsigmaKa < track.tpcNSigmaKa();
bool is_pr_excluded_TPC = track.tpcNSigmaPr() < mMinTPCNsigmaPr || mMaxTPCNsigmaPr < track.tpcNSigmaPr();
bool is_el_included_TOF = track.hasTOF() ? (mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl) : true;
bool is_el_included_TOF = track.hasTOF() ? (mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl && track.tofChi2() < mMaxChi2TOF) : true;
return is_el_included_TPC && is_mu_excluded_TPC && is_pi_excluded_TPC && is_ka_excluded_TPC && is_pr_excluded_TPC && is_el_included_TOF;
}

Expand All @@ -310,7 +309,7 @@ class DielectronCut : public TNamed
{
bool is_el_included_TPC = mMinTPCNsigmaEl < track.tpcNSigmaEl() && track.tpcNSigmaEl() < mMaxTPCNsigmaEl;
bool is_pi_excluded_TPC = track.tpcInnerParam() < mMaxPinForPionRejectionTPC ? (track.tpcNSigmaPi() < mMinTPCNsigmaPi || mMaxTPCNsigmaPi < track.tpcNSigmaPi()) : true;
bool is_el_included_TOF = track.hasTOF() ? (mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl) : true;
bool is_el_included_TOF = track.hasTOF() ? (mMinTOFNsigmaEl < track.tofNSigmaEl() && track.tofNSigmaEl() < mMaxTOFNsigmaEl && track.tofChi2() < mMaxChi2TOF) : true;
return is_el_included_TPC && is_pi_excluded_TPC && is_el_included_TOF;
}

Expand Down Expand Up @@ -339,6 +338,9 @@ class DielectronCut : public TNamed
case DielectronCuts::kTPCFracSharedClusters:
return track.tpcFractionSharedCls() <= mMaxFracSharedClustersTPC;

case DielectronCuts::kRelDiffPin:
return mMinRelDiffPin < (track.tpcInnerParam() - track.p()) / track.p() && (track.tpcInnerParam() - track.p()) / track.p() < mMaxRelDiffPin;

case DielectronCuts::kTPCChi2NDF:
return mMinChi2PerClusterTPC < track.tpcChi2NCl() && track.tpcChi2NCl() < mMaxChi2PerClusterTPC;

Expand Down Expand Up @@ -386,10 +388,12 @@ class DielectronCut : public TNamed
void SetMinNCrossedRowsTPC(int minNCrossedRowsTPC);
void SetMinNCrossedRowsOverFindableClustersTPC(float minNCrossedRowsOverFindableClustersTPC);
void SetMaxFracSharedClustersTPC(float max);
void SetRelDiffPin(float min, float max);
void SetChi2PerClusterTPC(float min, float max);
void SetNClustersITS(int min, int max);
void SetChi2PerClusterITS(float min, float max);
void SetMeanClusterSizeITS(float min, float max, float minP = 0.f, float maxP = 0.f);
void SetChi2TOF(float min, float max);

void SetPIDScheme(int scheme);
void SetMinPinTOF(float min);
Expand Down Expand Up @@ -452,12 +456,14 @@ class DielectronCut : public TNamed
float mMinChi2PerClusterTPC{-1e10f}, mMaxChi2PerClusterTPC{1e10f}; // max tpc fit chi2 per TPC cluster
float mMinNCrossedRowsOverFindableClustersTPC{0.f}; // min ratio crossed rows / findable clusters
float mMaxFracSharedClustersTPC{999.f}; // max ratio shared clusters / clusters in TPC
float mMinRelDiffPin{-1e10f}, mMaxRelDiffPin{1e10f}; // max relative difference between p at TPC inner wall and p at PV
int mMinNClustersITS{0}, mMaxNClustersITS{7}; // range in number of ITS clusters
float mMinChi2PerClusterITS{-1e10f}, mMaxChi2PerClusterITS{1e10f}; // max its fit chi2 per ITS cluster
float mMaxPinMuonTPConly{0.2f}; // max pin cut for muon ID with TPConly
float mMaxPinForPionRejectionTPC{1e10f}; // max pin cut for muon ID with TPConly
bool mRequireITSibAny{true};
bool mRequireITSib1st{false};
float mMinChi2TOF{-1e10f}, mMaxChi2TOF{1e10f}; // max tof chi2 per

float mMinDca3D{0.0f}; // min dca in 3D in units of sigma
float mMaxDca3D{1e+10}; // max dca in 3D in units of sigma
Expand Down
5 changes: 5 additions & 0 deletions PWGEM/Dilepton/Core/Dilepton.h
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Expand Up @@ -180,6 +180,7 @@ struct Dilepton {
Configurable<float> cfg_max_frac_shared_clusters_tpc{"cfg_max_frac_shared_clusters_tpc", 999.f, "max fraction of shared clusters in TPC"};
Configurable<float> cfg_max_chi2tpc{"cfg_max_chi2tpc", 4.0, "max chi2/NclsTPC"};
Configurable<float> cfg_max_chi2its{"cfg_max_chi2its", 5.0, "max chi2/NclsITS"};
Configurable<float> cfg_max_chi2tof{"cfg_max_chi2tof", 1e+10, "max chi2 TOF"};
Configurable<float> cfg_max_dcaxy{"cfg_max_dcaxy", 0.2, "max dca XY for single track in cm"};
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 0.2, "max dca Z for single track in cm"};
Configurable<bool> cfg_require_itsib_any{"cfg_require_itsib_any", false, "flag to require ITS ib any hits"};
Expand All @@ -188,6 +189,8 @@ struct Dilepton {
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
Configurable<float> cfg_min_p_its_cluster_size{"cfg_min_p_its_cluster_size", 0.0, "min p to apply ITS cluster size cut"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};

Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif = 4, kPIDML = 5]"};
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
Expand Down Expand Up @@ -642,6 +645,8 @@ struct Dilepton {
fDielectronCut.SetTrackMaxDcaZ(dielectroncuts.cfg_max_dcaz);
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
fDielectronCut.SetChi2TOF(0, dielectroncuts.cfg_max_chi2tof);
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);

// for eID
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
Expand Down
5 changes: 5 additions & 0 deletions PWGEM/Dilepton/Core/DileptonMC.h
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Expand Up @@ -160,6 +160,7 @@ struct DileptonMC {
Configurable<float> cfg_max_frac_shared_clusters_tpc{"cfg_max_frac_shared_clusters_tpc", 999.f, "max fraction of shared clusters in TPC"};
Configurable<float> cfg_max_chi2tpc{"cfg_max_chi2tpc", 4.0, "max chi2/NclsTPC"};
Configurable<float> cfg_max_chi2its{"cfg_max_chi2its", 5.0, "max chi2/NclsITS"};
Configurable<float> cfg_max_chi2tof{"cfg_max_chi2tof", 1e+10, "max chi2 TOF"};
Configurable<float> cfg_max_dcaxy{"cfg_max_dcaxy", 0.2, "max dca XY for single track in cm"};
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 0.2, "max dca Z for single track in cm"};
Configurable<bool> cfg_require_itsib_any{"cfg_require_itsib_any", false, "flag to require ITS ib any hits"};
Expand All @@ -168,6 +169,8 @@ struct DileptonMC {
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
Configurable<float> cfg_min_p_its_cluster_size{"cfg_min_p_its_cluster_size", 0.0, "min p to apply ITS cluster size cut"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};

Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif = 4, kPIDML = 5]"};
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
Expand Down Expand Up @@ -530,6 +533,8 @@ struct DileptonMC {
fDielectronCut.SetTrackMaxDcaZ(dielectroncuts.cfg_max_dcaz);
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
fDielectronCut.SetChi2TOF(0.0, dielectroncuts.cfg_max_chi2tof);
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);

// for eID
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
Expand Down
7 changes: 6 additions & 1 deletion PWGEM/Dilepton/Core/PhotonHBT.h
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Expand Up @@ -196,12 +196,15 @@ struct PhotonHBT {
Configurable<float> cfg_max_frac_shared_clusters_tpc{"cfg_max_frac_shared_clusters_tpc", 999.f, "max fraction of shared clusters in TPC"};
Configurable<float> cfg_max_chi2tpc{"cfg_max_chi2tpc", 4.0, "max chi2/NclsTPC"};
Configurable<float> cfg_max_chi2its{"cfg_max_chi2its", 5.0, "max chi2/NclsITS"};
Configurable<float> cfg_max_chi2tof{"cfg_max_chi2tof", 1e+10, "max chi2 TOF"};
Configurable<float> cfg_max_dcaxy{"cfg_max_dcaxy", 1.0, "max dca XY for single track in cm"};
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 1.0, "max dca Z for single track in cm"};
Configurable<float> cfg_min_its_cluster_size{"cfg_min_its_cluster_size", 0.f, "min ITS cluster size"};
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_p_its_cluster_size{"cfg_min_p_its_cluster_size", 0.0, "min p to apply ITS cluster size cut"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};

Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif = 4, kPIDML = 5]"};
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
Expand Down Expand Up @@ -552,6 +555,8 @@ struct PhotonHBT {
fDielectronCut.SetMeanClusterSizeITS(dielectroncuts.cfg_min_its_cluster_size, dielectroncuts.cfg_max_its_cluster_size, dielectroncuts.cfg_min_p_its_cluster_size, dielectroncuts.cfg_max_p_its_cluster_size);
fDielectronCut.SetTrackMaxDcaXY(dielectroncuts.cfg_max_dcaxy);
fDielectronCut.SetTrackMaxDcaZ(dielectroncuts.cfg_max_dcaz);
fDielectronCut.SetChi2TOF(0.0, dielectroncuts.cfg_max_chi2tof);
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);

// for eID
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
Expand Down
5 changes: 5 additions & 0 deletions PWGEM/Dilepton/Core/SingleTrackQC.h
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Expand Up @@ -121,6 +121,7 @@ struct SingleTrackQC {
Configurable<float> cfg_max_frac_shared_clusters_tpc{"cfg_max_frac_shared_clusters_tpc", 999.f, "max fraction of shared clusters in TPC"};
Configurable<float> cfg_max_chi2tpc{"cfg_max_chi2tpc", 4.0, "max chi2/NclsTPC"};
Configurable<float> cfg_max_chi2its{"cfg_max_chi2its", 5.0, "max chi2/NclsITS"};
Configurable<float> cfg_max_chi2tof{"cfg_max_chi2tof", 1e+10, "max chi2 TOF"};
Configurable<float> cfg_max_dcaxy{"cfg_max_dcaxy", 0.2, "max dca XY for single track in cm"};
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 0.2, "max dca Z for single track in cm"};
Configurable<bool> cfg_require_itsib_any{"cfg_require_itsib_any", false, "flag to require ITS ib any hits"};
Expand All @@ -129,6 +130,8 @@ struct SingleTrackQC {
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
Configurable<float> cfg_min_p_its_cluster_size{"cfg_min_p_its_cluster_size", 0.0, "min p to apply ITS cluster size cut"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};

Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif = 4, kPIDML = 5]"};
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
Expand Down Expand Up @@ -336,6 +339,8 @@ struct SingleTrackQC {
fDielectronCut.SetTrackMaxDcaZ(dielectroncuts.cfg_max_dcaz);
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
fDielectronCut.SetChi2TOF(0.0, dielectroncuts.cfg_max_chi2tof);
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);

// for eID
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
Expand Down
5 changes: 5 additions & 0 deletions PWGEM/Dilepton/Core/SingleTrackQCMC.h
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Expand Up @@ -124,6 +124,7 @@ struct SingleTrackQCMC {
Configurable<float> cfg_max_frac_shared_clusters_tpc{"cfg_max_frac_shared_clusters_tpc", 999.f, "max fraction of shared clusters in TPC"};
Configurable<float> cfg_max_chi2tpc{"cfg_max_chi2tpc", 4.0, "max chi2/NclsTPC"};
Configurable<float> cfg_max_chi2its{"cfg_max_chi2its", 5.0, "max chi2/NclsITS"};
Configurable<float> cfg_max_chi2tof{"cfg_max_chi2tof", 1e+10, "max chi2 TOF"};
Configurable<float> cfg_max_dcaxy{"cfg_max_dcaxy", 0.2, "max dca XY for single track in cm"};
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 0.2, "max dca Z for single track in cm"};
Configurable<bool> cfg_require_itsib_any{"cfg_require_itsib_any", false, "flag to require ITS ib any hits"};
Expand All @@ -132,6 +133,8 @@ struct SingleTrackQCMC {
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
Configurable<float> cfg_min_p_its_cluster_size{"cfg_min_p_its_cluster_size", 0.0, "min p to apply ITS cluster size cut"};
Configurable<float> cfg_max_p_its_cluster_size{"cfg_max_p_its_cluster_size", 0.0, "max p to apply ITS cluster size cut"};
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};

Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif = 4, kPIDML = 5]"};
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
Expand Down Expand Up @@ -388,6 +391,8 @@ struct SingleTrackQCMC {
fDielectronCut.SetTrackMaxDcaZ(dielectroncuts.cfg_max_dcaz);
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
fDielectronCut.SetChi2TOF(0.0, dielectroncuts.cfg_max_chi2tof);
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);

// for eID
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
Expand Down
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