🎓 SystemVerilog & VLSI Verification Journey

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💡 About This Repository

This repository documents my daily learning journey and projects in SystemVerilog and VLSI verification.

• 🎯 Goal: Become job-ready for VLSI verification roles at NVIDIA, Intel, Qualcomm, etc.
• 📝 Maintain daily logs summarizing concepts studied.
• 🛠️ Implement mini-projects to apply concepts practically.
• 🔄 Revise Verilog alongside SystemVerilog for a strong design foundation.

This repo serves as a learning diary + project portfolio.

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📅 Phase 1: Daily Log Tracker

Day	Date	Topics / Concepts Studied	Practical / Module Implemented	Status
1	19/10/2025	SystemVerilog: Built in functions	---
2	20/10/2025	SystemVerilog: Format Specifiers	---
3	21/10/2025	SystemVerilog: Strings	---
4	23/10/2025	SystemVerilog: enum	---
5	24/10/2025	SystemVerilog: Datatypes	---
6	25/10/2025	SystemVerilog: Copy Assignments	---
7	26/10/2025	SystemVerilog: Functions	---
8	27/10/2025	SystemVerilog: Tasks	---
9	28/10/2025	SystemVerilog: Exercise 1	4 bit counter

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🔁 Phase 2 – Restarting My SystemVerilog Journey

Fresh focus • Stronger consistency • Deeper understanding ⚡

After a short break for exams, I’m restarting my SystemVerilog & VLSI Verification streak from Day 1 — new mindset, same mission 🚀
(Previous streak: Days 1–9 ✅ Completed)

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📅 Phase 2: Daily Log Tracker (Restart from 09 Nov 2025)

Day	Date	Topics / Concepts Studied	Practical / Module Implemented	Status
1	10/11/2025	SystemVerilog: Inheritance	---
2	11/11/2025	SystemVerilog: Polymorphism	---
2	12/11/2025	SystemVerilog: Loops	---

🚀Phase 3 – A Fresh Restart

Not a pause — just a different direction. Hackathons, projects, and parallel learning kept me growing. Now I’m back to SystemVerilog from Day 1 — sharper, clearer, and more focused than ever 🔥

📅 Phase 3: Daily Log Tracker (Restart from 17 Nov 2025)

Day	Date	Topics / Concepts Studied	Practical / Module Implemented	Status
1	17/11/2025	SystemVerilog: Arrays Part-1	---
2	18/11/2025	SystemVerilog: Packed and Unpacked Arrays(Part 1)	---
3	19/11/2025	SystemVerilog: Associative arrays	---

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🚀 Phase 4 — Practical SystemVerilog Verification

Hands-on coding • Testbenches • Digital design fundamentals

During previous phases, I focused entirely on SystemVerilog theory. Now, in Phase 4, I'm shifting to full practical verification — writing testbenches, building architectures, and implementing real modules.

This phase boosts both digital design fundamentals and SystemVerilog coding skills.

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📅 Phase 4: Practical Log Tracker (Starting: 01 Dec 2025)

Day	Date	Module / Concept	Testbench Component	Status
1	01/12/2025	Half Adder	Simple testbench
2	02/12/2025	Full Adder	Simple testbench
3	08/12/2025	4-bit Adder	Interface + TB integration
4	09/12/2025	Subtractor	Functional coverage
5	10/12/2025	Comparator	Assertions
6	11/12/2025	MUX (2:1 / 4:1)	Constrained random TB
7	12/12/2025	Decoder (3:8)	Self-checking TB
8	13/12/2025	Counter (4-bit)	Scoreboard refinement
9	14/12/2025	FSM (Moore)	Reference model
10	15/12/2025	FSM (Mealy)	Coverage closure

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🧩 Phase 4 Goals

• Build modular testbenches for small digital blocks
• Strengthen Driver ↔ Monitor ↔ Scoreboard concepts
• Learn how to write self-checking testbenches
• Start using randomization + coverage + assertions in real examples
• Prepare solid foundation for UVM (Phase 5)

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🛠 Deliverables in Phase 4

Each module will include:

• SystemVerilog Design Code (DUT)
• Complete Testbench Architecture
• Driver / Monitor / Scoreboard implementation
• Waveform screenshots
• Assertions
• Functional coverage
• Explanation of TB flow

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🧩 How I Use This Repo

• Daily Logs: Summarize concepts studied and key takeaways.
• Project Commits: Upload modules/project code once completed.
• Waveforms & Coverage: Include screenshots or .vcd files for verification evidence.

Learning by doing is the main focus — concepts are reinforced through practical implementation.

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🛠 Tools & Technology Stack

• HDL: Verilog, SystemVerilog
• Simulation: Synopsys VCS, ModelSim, QuestaSim
• Waveform Viewer: Verdi, GTKWave
• Editor/IDE: VS Code, Sublime Text
• Version Control: Git & GitHub