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Now that I have a pretty good idea on the design of the CPU, it's time to get started on the hardware. The first step is generating a clock signal. While the clock is not technically a part of the CPU itself, it is a key input into the system and is necessary for any testing of the hardware.
Once this design is fully realized and implemented on a PCB, it should be able to run at a clock rate of several MHz. However, until then, I will want to run it at a much lower speed for testing and debugging. I have three different clock generator circuits.
The manual clock generator makes it easy to test and verify the functionality of the circuits as I build them and can also be used for debugging where single-stepping the clock will be useful.
The manual clock circuit is just two push buttons debounced with an SR-latch implemented with two NAND gates from a 74HC00 chip and a couple pull-up resistors.
This circuit lets me manually toggle clock transitions from low-to-high and high-to-low as needed to check the circuit operation.
This setup uses an Arduino UNO and a simple sketch that lets me select a desired clock rate (from 31 Hz to 65535 Hz). This is useful for running tests that would be too cumbersome to manually toggle the clock (e.g., testing that the PC counter chips correctly cascade the output of the 4-bit counters to the next counter block). It also gives me an indication that the circuit is robust enough to move on to MHz range testing.
For clock rates in the MHz range, I plan to use a TTL Clock Oscillator. These parts integrate the resonator and oscillator components along with a buffer circuit into a single package, rather than having to deal with multiple discrete parts to create the clock signal.
Once I started working on the hardware for my original design, I quickly realized that two-byte opcodes were not going to work (or were at least going to make the hardware much more complicated than I envisioned). I needed to move to a single-byte instruction length. See the wiki pages under the "Current Design" heading for the updated design. The old design is available under the "Previous Design" heading. I have updated the emulator/disassembler to the Version 2 design.
I have completed the implementation and limited testing of an emulator and disassembler for my CPU design.
I have created and documented an initial design including register list, addressing modes, supported instructions, opcode structure and opcode list. See the wiki for details.
Starting on my homemade CPU. Created this repo and associated wiki. Getting started on the design.
- Online logic-gate schematic generator tool
- EasyEda PCB design software, pro version
- Clock circuit schematics: manual