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AnilS454/README.md

Hi, I'm Anil — VLSI Engineer 👋

I build silicon from RTL to GDSII — specializing in ASIC physical design, FPGA implementation and AI accelerator architecture on open-source EDA flows.

What I built

  • ASIC Physical Design — Full PnR on SKY130 using OpenLane2 + OpenROAD, DRC/LVS clean
  • FPGA Acceleration — Systolic array AI accelerator on ZCU104 Zynq UltraScale+

Key Projects

Project Stack Status
pe-asic-sky130 OpenLane2 · OpenROAD · SKY130 · OpenSTA ✅ GDS + Timing Clean
systolic-array-fpga-zcu104 Vivado · Zynq · SystemVerilog ✅ Post-Impl Simulation

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  1. pe-asic-sky130 pe-asic-sky130 Public

    Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2

    Perl

  2. systolic-array-fpga-zcu104 systolic-array-fpga-zcu104 Public

    8x8 Systolic Array AI Accelerator - Non-pipelined single-cycle MAC PE Systolic array uses wave-skew dataflow for data movement between PEs

    SystemVerilog