Popular repositories Loading

1. Workshop-RTL-design-using-Verilog-with-SKY130-Technology Workshop-RTL-design-using-Verilog-with-SKY130-Technology Public

   2

2. STA STA Public

   Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculate…

   1 1

3. iiitb_sqd_1010 iiitb_sqd_1010 Public

   Verilog 1

4. BigSpicy BigSpicy Public

   Python

5. iiitb_sqd_1010_mpw8 iiitb_sqd_1010_mpw8 Public

   Verilog 1