FS-Cache and version bump to R9.6-RC01

.gitignore

@@ -2155,3 +2155,4 @@ workbench/tools/InstallAROS/strings.h
 workbench/tools/SysExplorer/strings.h
 workbench/tools/WiMP/strings.h
 arch/m68k-amiga/boot/romlog.txt
+arch/m68k-amiga/boot/romlog.txt

arch/m68k-amiga/boot/romlog.txt

@@ -1,3 +1,3 @@
 Idx Name          Size      VMA       LMA       File off  Algn
-  0 .rom          0007a2a0  00f80000  00f80000  00080000  2**2
-  1 .ext          0007d90e  00e00000  00e00000  00002000  2**2
+  0 .rom          0007a2a0  00f80000  00f80000  00082000  2**2
+  1 .ext          0007f23e  00e00000  00e00000  00002000  2**2

arch/m68k-amiga/devs/sagasd/sd.h

@@ -51,7 +51,7 @@
 #define IOStdReq(io) ((struct IOStdReq *)io)
 
 #if APOLLO_DEBUG
-#define DEBUG 0
+#define DEBUG 1
 #else
 #define DEBUG 0
 #endif

rom/devs/ata/ata.h

@@ -39,14 +39,7 @@
 #define TASK_PRI                10
 #define TIMEOUT                 30
 
-#if VAMPIRECARDSERIES==2
-#define CACHE_SIZE_BITS         14      /* V2 = 2^14 * 512 byte blocks = 8Mb */
-#else
-#define CACHE_SIZE_BITS         17      /* V4 = 2^17 * 512 byte blocks = 64Mb */
-#endif
-
-#define CACHE_SIZE              (1<<CACHE_SIZE_BITS)
-#define CACHE_MASK              (CACHE_SIZE-1)
+#define CACHE_MASK8             (((1<<20)>>3)-1)
 
 #if APOLLO_DEBUG
 #define DEBUG 1
@@ -121,6 +114,8 @@ struct ataBase
      */
     UBYTE                    	*ata_CacheData;
     UQUAD                   	*ata_CacheTags;
+    ULONG                       myway;
+    ULONG                       CACHE_SIZE8;
 
     ULONG                   	ata_ItersPer100ns;
 

rom/devs/ata/ata_init.c

@@ -221,6 +221,19 @@ static int ATA_init(struct ataBase *ATABase)
 
     DATAINIT(bug("[ATA--] %s: MemPool @ %p\n", __func__, ATABase->ata_MemPool));
 
+    // Was bin ich?
+    //
+    ULONG CACHE_SIZE = (1<<20); // 512 MB
+    volatile UBYTE *wasbinich=0xDFF3FC;
+    UBYTE ichbin = *wasbinich;
+    if ( ichbin==0x08) {  // Einhorn
+      CACHE_SIZE = (1<<20);  // 512 MB
+    }else{
+      CACHE_SIZE = (1<<17);  // 64 MB
+    } 
+    ATABase->CACHE_SIZE8 = (CACHE_SIZE>>3);  // set size of 1 way of (8way cache)
+
+
     /*
      * ata drive cache memory allocation
      */

rom/devs/ata/scsiemu.c

@@ -52,26 +52,80 @@ static UBYTE scsi_read32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG l
      {
          struct ata_Bus *bus = unit->au_Bus;
          struct ataBase *base = bus->ab_Base;
-         ULONG unitNum = unit->au_UnitNum;
+         ULONG CACHE_SIZE8 = base->CACHE_SIZE8;
+
+	 ULONG unitNum = unit->au_UnitNum;
+
+         base->myway = ( base->myway+1) & 7;  // 8 way for good
+
 
          ULONG start;
          ULONG i;
          for (start = 0, i = 0; i < len; i++)
          {
-             ULONG blockAdr = (offset + i) & CACHE_MASK;
-             UQUAD blockTag = (offset + i) & ~CACHE_MASK;
+             ULONG blockAdr = (offset + i) & (CACHE_SIZE8-1);  //MASK
+             ULONG blockAdr0 = blockAdr;
+             ULONG blockAdr1 = blockAdr + CACHE_SIZE8;
+             ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2;
+             ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3;
+             ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4;
+             ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5;
+             ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6;
+             ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7;
+
+
+
+             UQUAD blockTag = (offset + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum;
+                // 8 way disk cache 512 MB default
+                //
+             if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr0] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr0*512, data + i*512, 512);
+                 start = i + 1;
 
-             if ((unitNum < (1<<9)) &&
-                 (base->ata_CacheTags[blockAdr] == (blockTag | unitNum))) /* cache hit */
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr1] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr1*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr2] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr2*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr3] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr3*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr4] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr4*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr5] == blockTag )) /* cache hit */
              {
-                 CopyMem(base->ata_CacheData + blockAdr*512, data + i*512, 512);
+                 CopyMem(base->ata_CacheData + blockAdr5*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr6] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr6*512, data + i*512, 512);
+                 start = i + 1;
+             }
+             else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr7] == blockTag )) /* cache hit */
+             {
+                 CopyMem(base->ata_CacheData + blockAdr7*512, data + i*512, 512);
                  start = i + 1;
              }
              else
              {
                  i = len;
                  break;
-             }    
+             }
+
+
          }
          if (start != i)
          {
@@ -86,12 +140,14 @@ static UBYTE scsi_read32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG l
 
              for (ULONG j = start; j < i; j++)
              {
-                 ULONG blockAdr = (offset + j) & CACHE_MASK;
+
+                 ULONG blockAdr = (offset + j) & (CACHE_SIZE8-1);
+                 blockAdr  += CACHE_SIZE8 * (base->myway & 7);  // random 8 way
                  CopyMem(data + j*512, base->ata_CacheData + blockAdr*512, 512);
-                 blockAdr = (offset + j) & CACHE_MASK;
-                 ULONG blockTag = (offset + j) & ~CACHE_MASK;
-                 base->ata_CacheTags[blockAdr] = blockTag | unitNum;
-             }
+                 UQUAD blockTag = (offset + j) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum;
+                 base->ata_CacheTags[blockAdr] = blockTag;
+
+	     }
          }
          *outlen = len << unit->au_SectorShift;
          return io_Error;
@@ -118,12 +174,35 @@ static UBYTE scsi_write32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG
     {
         struct ata_Bus *bus = unit->au_Bus;
         struct ataBase *base = bus->ab_Base;
-
-        for (int i = 0; i < len; i++)
+        ULONG CACHE_SIZE8 = base->CACHE_SIZE8;
+
+	ULONG unitNum = unit->au_UnitNum;
+
+        for (int i = 0; i < len ; i++ )
         {
-            ULONG blockAdr = (offset + i) & CACHE_MASK;
-            base->ata_CacheTags[blockAdr] = 0xfffffffffffffffful;
+            ULONG blockAdr = (offset + i) & (CACHE_SIZE8-1);  // MASK
+            ULONG blockAdr0 = blockAdr;
+            ULONG blockAdr1 = blockAdr + CACHE_SIZE8;
+            ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2;
+            ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3;
+            ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4;
+            ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5;
+            ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6;
+            ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7;
+
+            UQUAD blockTag = (offset + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum;
+            if( base->ata_CacheTags[blockAdr0] == blockTag ){  base->ata_CacheTags[blockAdr0] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr1] == blockTag ){  base->ata_CacheTags[blockAdr1] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr2] == blockTag ){  base->ata_CacheTags[blockAdr2] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr3] == blockTag ){  base->ata_CacheTags[blockAdr3] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr4] == blockTag ){  base->ata_CacheTags[blockAdr4] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr5] == blockTag ){  base->ata_CacheTags[blockAdr5] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr6] == blockTag ){  base->ata_CacheTags[blockAdr6] = 0xfffffffffffffffful; }
+            if( base->ata_CacheTags[blockAdr7] == blockTag ){  base->ata_CacheTags[blockAdr7] = 0xfffffffffffffffful; }
+
         }
+
+
     }
 
      err = unit->au_Write32(unit, offset, len, data, outlen);

version

@@ -1 +1 @@
-Release 9.51
+Release 9.6-RC01

workbench/libs/lowlevel/elapsedtime.c

@@ -49,7 +49,7 @@
     SubTime(&b, tlast);
     *tlast = a;
 
-    return b.tv_secs*1000 + b.tv_micro/1000;
+    return (b.tv_secs << 16) | (b.tv_micro*1024/15625);  // Patch by Apollo Team (@Morten)
 
     AROS_LIBFUNC_EXIT
 } /* ElapsedTime */

workbench/system/find/findgroup_class.h

@@ -2,10 +2,25 @@
 #define FINDGROUP_CLASS_H
 
 /*
-    Copyright � 2016, The AROS Development Team. All rights reserved.
+    Copyright � 2016, The AROS Development Team. All rights reserved.
     $Id$
 */
 
+#if APOLLO_DEBUG
+#define DEBUG 1
+#else
+#define DEBUG 0
+#endif
+
+#if DEBUG
+#include <aros/debug.h>
+#define DD(x) x
+#define bug kprintf
+#else
+#define DD(x)
+#define bug 
+#endif
+
 #include <exec/types.h>
 #include <libraries/mui.h>