🏠
Working from home
Electronics and Communication Engineer. Having great passion towards learning.
- Chennai, Tamil Nadu, India
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Pipelined-AES-256
Pipelined-AES-256 PublicThis is a course project for EE705 Spring 2024. This has been implemented using DE2-115 and has been tested using Nios-II Soft Processor
Verilog
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ECG-Data-Pynq-Z2
ECG-Data-Pynq-Z2 PublicThis is a course project for EE712 Embedded Systems to indicate the usage of a sensor and show it real time in monitor via HDMI.
VHDL
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tt_fibonacci
tt_fibonacci PublicForked from sellicott/sellicott_fib_seq
Tiny Tapeout Fibonacci sequence generator example project
Verilog
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