Ex No: 0 - Design & Implementation of 2-Input NAND Gate Using Cadence EDA Tools

Aim

The aim is to design and simulate a 2-input CMOS NAND gate using Cadence EDA tools, analyze its electrical characteristics, and understand fundamental CMOS logic gate design principles through schematic design and simulation approaches.

Tools Required

Cadence EDA Suite

• Virtuoso Schematic Editor (for circuit design)
• Spectre Simulator (for circuit simulation)

Process Design Kit (PDK)

• CMOS technology library (e.g., 180nm, 45nm node)

Computer System Requirements

• Minimum 4GB RAM
• Multi-core processor

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Procedure

1. Launch Cadence Virtuoso Environment

• Open Cadence Virtuoso and set up the working library.
• Create a new schematic cell view for the 2-input NAND gate.

2. Schematic Design

• Select NMOS and PMOS transistors from the technology library.
• PMOS Network: Connect two PMOS transistors in parallel between VDD and the output node.
• NMOS Network: Connect two NMOS transistors in series between GND and the output node.
• Join the gate terminals of one PMOS and one NMOS transistor for the first input (A) and the second set for the second input (B).
• Apply input voltage sources (Vdc, Vpulse) to simulate digital logic inputs.

3. Simulation

• Check the design for errors and proceed with the simulation setup.
• Launch the Analog Design Environment (ADE).
• Configure transient analysis for time-domain response.
• Set up DC analysis to observe static characteristics.
• Use the Spectre simulator to perform transient and DC analyses.

4. Waveform Analysis

• Observe the output voltage waveform for different input voltage combinations (00, 01, 10, 11).

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Circuit Diagram

2-Input NAND Gate CMOS Circuit

Schematic of 2-Input NAND Gate

Transient Response Setup

Output

Transient Analysis Output:

Results

1. Successfully designed the 2-input NAND gate schematic using Cadence EDA tools.
2. The simulation results verified the NAND logic function, where the output remains HIGH except when both inputs are HIGH (A = 1, B = 1, Y = 0).

Ex No: 0 - Design & Implementation of 2-Input NOR Gate Using Cadence EDA Tools

Aim

The aim is to design and simulate a 2-input CMOS NOR gate using Cadence EDA tools, analyze its electrical characteristics, and understand fundamental CMOS logic gate design principles through schematic design and simulation approaches.

Tools Required

Cadence EDA Suite

• Virtuoso Schematic Editor (for circuit design)
• Spectre Simulator (for circuit simulation)

Process Design Kit (PDK)

• CMOS technology library (e.g., 180nm, 45nm node)

Computer System Requirements

• Minimum 4GB RAM
• Multi-core processor

Procedure

1. Launch Cadence Virtuoso Environment

• Open Cadence Virtuoso and set up the working library.
• Create a new schematic cell view for the 2-input NOR gate.

2. Schematic Design

• Select NMOS and PMOS transistors from the technology library.
• PMOS Network: Connect two PMOS transistors in series between VDD and the output node.
• NMOS Network: Connect two NMOS transistors in parallel between GND and the output node.
• Join the gate terminals of one PMOS and one NMOS transistor for the first input (A) and the second set for the second input (B).
• Apply input voltage sources (Vdc, Vpulse) to simulate digital logic inputs.

3. Simulation

• Check the design for errors and proceed with the simulation setup.
• Launch the Analog Design Environment (ADE).
• Configure transient analysis for time-domain response.
• Set up DC analysis to observe static characteristics.
• Use the Spectre simulator to perform transient and DC analyses.

4. Waveform Analysis

• Observe the output voltage waveform for different input voltage combinations (00, 01, 10, 11).

Circuit Diagram

2-Input NOR Gate CMOS Circuit

Schematic of 2-Input NOR Gate

Transient Response Setup

Output

Transient Analysis Output:

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Results

1. Successfully designed the 2-input NOR gate schematic using Cadence EDA tools.
2. The simulation results verified the NOR logic function, where the output remains LOW except when both inputs are LOW (A = 0, B = 0, Y = 1).