Program Counter is very important part of any microprocessor or microcontroller. Its job is the store the address of next instruction to be executed. we will complete this project by 2 different approaches.
We will first write a verilog code for PC, and test it on Xilinx Vivado software (Software verification). Next step includes burning bit file of that code into FPGA board and testing the functionality (Hardware Verfication). Then we will import the code on Cadence software. We will simulate the code, generate netlist & finally make layout.
No need to write Verilog Code. Directly design the circuit on Cadence Software. Botom up design methodology is used. Transmission gate design style is used. Simulate the code using DC analysis & Transient Analysis. Create Layout of the circuit.
| Tool | Description |
|---|---|
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Vivado is used for programming FPGA and SoC devices. It offers tools for synthesis, implementation, simulation, and verification of digital designs. It supports various languages like Verilog, VHDL, and SystemVerilog. |
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Cadence Design Systems provides a wide range of products and services including digital integrated circuit design, functional verification, custom IC design, PCB layout and design, and system design enablement. |
| Tool | Description |
|---|---|
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Xilinx Spartan 7 chip, 8 seven segment displays, 16 slide switches, 4 push buttons, 16 LED's, 4 Pmods |
Output on Vivado Tool
Output on NCsim, Cadence
Output on Genus, Cadence
Output on Innovus, Cadence
Output on FPGA board
Output on Virtuoso, Cadence
