RiscV-CPU

This repo is for little term, the goal is to develop a risc-v based cpu with pipeline struct

Update Log

• ZoroGH, Init
• LBW, update instructions & jmp, 20230830

Instructions

• add
• sub
• addi
• mul
• mulh
• beq
• bne
• blt
• bge
• jal
• sw
• lw
• xor
• and
• or
• lui
• auipc

Module interface definition

Fetch

input clk,
input rst,
input clr,
input jmp_en,
input jmp_addr,
// ouptut 
output [31:0] ins

Decode

input clk,
input rst,
input clr,
input [31:0] ins,
output opcode,
output rs1,
output rs2,
output rd,
output offset,
output immediate

Execute

    input clk,
    input rst,
    input [4:0] optype,
    input [4:0] rs1,
    input [4:0] rs2,
    input [4:0] rd,
    input [31:0] offset,
    input [31:0] immediate,

    output [31:0] mem_addr,     // addr for load or store
    input  [31:0] mem_data,     // data from mem(for load)
    output [31:0] write_data,   // data to mem (for store)
    output load_en,
    output store_en,

    output jmp_en,
    output jmp_addr,

    output res,// result
    output clr

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TODO List

• state machine
• waveform graph
• interface
• simulation result

Resource

• wave
• state machine
• tiny_riscv