[cheriot] Add an R_RISCV_CHERIOT_CCALL reloc #114
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Supersedes #114 |
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Fixes #106 |
This was referenced Feb 15, 2025
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This also needs documenting in the cheriot-sail repo (where the ABI spec lives). |
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Way ahead of you: CHERIoT-Platform/cheriot-sail#97 |
davidchisnall
approved these changes
Feb 18, 2025
This is needed because Cheriot uses 11-bit shifts on AUIPCC (differing from normal RISC-V CHERI), and requires that the HI and LO relocs offset the target in the same direction. This is meant to be handled for all of Cheriot via R_RISCV_CHERIOT_COMPARTMENT_HI and R_RISCV_CHERIOT_COMPARTMENT_LO_I, but that is complicated by the simultaneous need to relax calls in (almost) all situations, which requires using R_RISCV_CHERI_CCALL. The solution is to add a new reloc that relaxes like R_RISCV_CHERI_CCALL, but relocates via R_RISCV_CHERIOT_COMPARTMENT_HI / R_RISCV_CHERIOT_COMPARTMENT_LO_I.
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This is needed because Cheriot uses 11-bit shifts on AUIPCC (differing from normal RISC-V CHERI), and requires that the HI and LO relocs offset the target in the same direction. This is meant to be handled for all of Cheriot via R_RISCV_CHERIOT_COMPARTMENT_HI and R_RISCV_CHERIOT_COMPARTMENT_LO_I, but that is complicated by the simultaneous need to relax calls in (almost) all situations, which requires using R_RISCV_CHERI_CCALL. The solution is to add a new reloc that relaxes like R_RISCV_CHERI_CCALL, but relocates via R_RISCV_CHERIOT_COMPARTMENT_HI / R_RISCV_CHERIOT_COMPARTMENT_LO_I.