GitHub - Calebp98/systolic-array: 4x4 output-stationary systolic array with MNIST inference pipeline in Verilog · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.claude		.claude
mnist		mnist
rtl		rtl
tb		tb
.gitignore		.gitignore
Makefile		Makefile
requirements.txt		requirements.txt
run_tests.sh		run_tests.sh

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4x4 output-stationary systolic array with MNIST inference pipeline in Verilog

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