FPGA RTL Template (Arty A7-35 default)

This repository is a reusable FPGA RTL template. The default example targets arty_a7_35 and should run out of the box for lint/sim.

Template Usage Steps

1. Copy local machine config:

   cp config.local.mk.example config.local.mk

2. Select board (default example):

   ./scripts/use_board.sh arty_a7_35

3. Run typical flow:

   make lint
   make sim
   make xdc
   make vivado

Configuration

• constraints/boards/<board>/...: store real board constraints (pins.csv, clocks.xdc, optional board-specific files).
• constraints/pins.csv and constraints/clocks.xdc: active board copy used by build flow.
• project.mk: project-level defaults (PROJECT/TOP/PART/BOARD).
• config.local.mk: machine-local config (e.g. VIVADO_BAT), intentionally untracked.

Notes

• constraints/top.xdc is generated by make xdc.
• CI only runs make lint and make sim; Vivado is not run in CI.