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1. RISC-Sim-by-Rashid RISC-Sim-by-Rashid Public

   RISCV (RV32I) Simulator and Debugger to help students learn the architecture by writing assembly and watch state of the CPU registers and memory.

   Python 6

2. osoc1_core_sv osoc1_core_sv Public

   This is system verilog implementation of Osoc1

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3. chip-design-website chip-design-website Public

   Curriculum website for the Chip Design with Rashid channel

   HTML

4. osoc1_core_uarch osoc1_core_uarch Public

   RV32 Core of RISCV is implemented in Hardware; Initially in Python , later in System Verilog

   Jupyter Notebook