macrostrip

Generate LEF-consistent frame-view GDS files for NDA-protected hard macros, so you can ship something to a tapeout backend without shipping your real layout — and swap the real macro back in once the final chip GDS returns.

Why

Hard-macro IP is often under NDA: the vendor gives you a LEF (pin locations, blockages), a Liberty file (timing/power), and a black-box Verilog stub — but not the real GDS. A chip-level place-and-route flow, however, needs some GDS for the macro so that chip-level DRC, antenna, density, and LVS can see a plausible outline and pin set.

macrostrip takes your real macro GDS and produces a reduced "frame view" that strips everything from the real macro except what chip-level LVS and DRC need to pass. Placement, routing, and PDN run against LEF and never read the GDS; the frame only matters at tapeout (cell substitution) and at LVS (pin identification via text labels).

What's kept:

• Pin shapes on the layers LEF declares — geometrically identical to the real macro.
• A text label on each pin shape with the LEF pin name. Same-name labels across shapes signal "same internal net" to LVS.
• Power/ground pin shapes on the declared power layers.
• Optional LEF OBS (routing obstructions above the macro).
• Optional outline polygon on a PR-boundary layer — emitted only if the layer map declares one (PDKs vary).
• Optional density fill and well-continuity rectangles — opt-in.

Everything else — internal routing, standard cells, any shape not visible at the boundary — is dropped. Typical output is 2 cells: the macro's top cell and the $MACROSTRIP_V1 spec-version marker. Density-fill configs add a few small $MACROSTRIP_FILL_* sub-cells (one per layer/size).

Once the backend returns the finished chip GDS with your frame view embedded, macrostrip swap replaces the frame cell's contents with the real macro, giving you a tapeout-ready GDS without the proprietary layout ever leaving your premises.

Use cases

• Submitting to a cloud-hosted tapeout flow while keeping an NDA macro private.
• Running a third-party P&R / signoff flow on a machine that shouldn't see the real layout.
• Academic / MPW flows with encrypted hard IP.

The tool is independent of any particular backend — it produces plain GDS. ChipFlow's cloud builder consumes frame-view GDS produced by this tool; any other flow that can accept a GDS black box can too.

Status

Reference implementation of SPEC.md. All five subcommands working end-to-end against real open-source hard macros (IHP SG13G2 and GF180MCU SRAMs, via their respective open PDKs). If you have strict audit requirements you can implement your own conformant frame generator and still interoperate with any backend that validates against the spec.

Install

pip install macrostrip

macrostrip uses KLayout (via the klayout PyPI package) for GDS I/O, LEF parsing, and geometry.

Subcommands

macrostrip frame     — real macro GDS + LEF  →  frame-view GDS (+ blackbox.json)
macrostrip validate  — check a frame-view GDS against SPEC.md (and, optionally, LEF)
macrostrip swap      — replace a frame-view cell in a chip GDS with the real macro
macrostrip blackbox  — LEF  →  tool-agnostic *.blackbox.json
macrostrip stub      — LEF  →  Verilog black-box module

frame and validate need a layer map (below). swap, blackbox, and stub don't touch GDS geometry from the LEF reader's perspective, so they skip it.

Produce a frame view

macrostrip frame \
    --layer-map pdk.map \
    --lef my_macro.lef \
    --top MY_MACRO \
    --output my_macro.frame.gds \
    my_macro.gds

Also writes my_macro.frame.blackbox.json next to the GDS. Pass --no-blackbox to suppress.

Opt-in DRC extras

The defaults give you enough for chip-level LVS (pin shapes + labels). Two families of DRC-driven extras are opt-in:

# OpenROAD-compatible density-fill config (same schema as ORFS's
# platform fill.json — reuse the one your PDK ships). Fill is emitted
# as hierarchical sub-cells named $MACROSTRIP_FILL_*.
macrostrip frame ... --fill-config orfs/platforms/ihp-sg13g2/fill.json

# Boundary-covering rectangle on a well layer, for chip-level
# well-continuity DRC. One rect per --well-layer:
macrostrip frame ... --well-layer NWell

Neither is declared in LEF, so both are driven entirely by your PDK's DRC deck requirements.

Validate a frame view

# Structural checks only (marker, single top cell, no forbidden cells):
macrostrip validate --layer-map pdk.map my_macro.frame.gds

# Plus per-pin equivalence against a LEF:
macrostrip validate --layer-map pdk.map --lef my_macro.lef --top MY_MACRO \
    my_macro.frame.gds

Exits 0 on pass, 1 on validation errors, 2 on a fatal input problem.

Swap the real macro back in

macrostrip swap \
    --cell MY_MACRO \
    --output chip.tapeout.gds \
    chip.final.gds \
    my_macro.gds

No layer map required. The swap is keyed on cell name. It refuses if the real macro GDS itself carries the $MACROSTRIP_V1 marker (i.e., you passed a frame view where a real macro was expected).

Companion artifacts

# Tool-agnostic JSON description (downstream flows consume this
# without re-parsing LEF):
macrostrip blackbox --lef my_macro.lef --top MY_MACRO \
    --output my_macro.blackbox.json

# Verilog black-box module (port list, bus widths, directions):
macrostrip stub --lef my_macro.lef --top MY_MACRO \
    --output my_macro.v

Layer map file

A simple whitespace-separated text file mapping each LEF layer name to a GDS (layer, datatype) pair.

# lef_name      gds_layer   datatype
Metal1          34          0
Metal2          36          0
prBoundary      235         4    # optional — see below

A prBoundary entry is optional. When present, frame emits the macro outline rectangle on that layer and validate cross-checks it against LEF SIZE. When absent, both steps skip the outline — this is the right choice for PDKs (e.g., GF180MCU) that have no canonical PR-boundary layer. Flows whose DRC decks or P&R tools expect an outline on a specific layer should declare it.

Fixtures for IHP SG13G2 (ihp_sg13g2.map, declares prBoundary at (189, 0)) and GF180MCU (gf180mcu.map, no outline) live under tests/fixtures/.

License

BSD-2-Clause. See LICENSE.