4-bit ALU (Arithmetic Logic Unit)

A Verilog implementation of a 4-bit Arithmetic Logic Unit that performs basic arithmetic and logical operations.

Author

• Sanskaar
• GitHub: CodeFreak2186

Project Repository

https://github.com/CodeFreak2186/4-bit-ALU.git

Features

This 4-bit ALU implements the following operations:

• Addition (4-bit)
• Subtraction (4-bit)
• Logical Operations:
  • AND
  • OR
  • XOR
  • NOT

Project Structure

├── alu_gate.json      # Digital circuit configuration
├── alu_gate.png      # Circuit diagram (PNG format)
├── alu_gate.svg      # Circuit diagram (SVG format)
├── alu_gate.v        # Top-level ALU gate implementation
├── synth.ys          # Synthesis script
├── src/
│   ├── add4.v       # 4-bit adder module
│   ├── alu_4bit.v   # Main ALU implementation
│   ├── alu_mux.v    # Multiplexer for ALU operations
│   ├── flag_unit.v  # Flag generation unit
│   ├── logic4.v     # Logic operations implementation
│   └── sub4.v       # 4-bit subtractor module
└── tb/
    └── alu4_tb.v    # Testbench for ALU verification

Prerequisites

To run and simulate this project, you need:

1. Icarus Verilog (iverilog) - for simulation
2. GTKWave - for viewing waveforms
3. Yosys - for synthesis (optional)

How to Run

1. Simulation:

   # Compile the design and testbench
   iverilog -o alu_sim tb/alu4_tb.v src/*.v
   
   # Run the simulation
   vvp alu_sim
   
   # View waveforms
   gtkwave alu4_tb.vcd

2. Synthesis (if using Yosys):

   # Run synthesis
   yosys -s synth.ys

Test Results

The simulation results can be found in alu4_results.txt file.

License

This project is open source and available under the MIT License.