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[arch/memdomain] refractor: finish the back-end arch unification#20

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Mikemy666 merged 1 commit into
DangoSys:mainfrom
Mikemy666:main
Dec 18, 2025
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[arch/memdomain] refractor: finish the back-end arch unification#20
Mikemy666 merged 1 commit into
DangoSys:mainfrom
Mikemy666:main

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  1. Achieve unified backend architecture.
  2. Modify the readme reference file.
  3. Set up the translator IO framework; currently, it supports pass-through functionality.

Copilot AI review requested due to automatic review settings December 18, 2025 08:37
@Mikemy666 Mikemy666 merged commit c8ca497 into DangoSys:main Dec 18, 2025
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Pull request overview

This PR refactors the memory domain backend to achieve a unified architecture by consolidating separate scratchpad and accumulator banks into a single AccMonitor abstraction. The changes eliminate the previously separate AccBank module and simplify the memory controller's connection topology by removing intermediate ToPhysicalLine translation layers, implementing pass-through functionality in the Translator instead.

Key Changes:

  • Introduced AccMonitor.scala which wraps SramBank with an accumulation pipeline (AccPipe) and read router (AccReadRouter), replacing the former AccBank.scala
  • Unified all memory banks in Scratchpad to use AccMonitor, combining sp_banks and acc_banks into a single pool with consistent parameters
  • Removed ToPhysicalLine modules from MemDomain, connecting translator outputs directly to scratchpad IO

Reviewed changes

Copilot reviewed 6 out of 6 changed files in this pull request and generated 6 comments.

Show a summary per file
File Description
AccMonitor.scala New unified bank monitor with accumulation support; adds metadata fields (rob_id, bank_id, is_acc) to read/write IOs
AccBank.scala Deleted - functionality moved to AccMonitor.scala
Scratchpad.scala Refactored to instantiate AccMonitor for all banks; unified interface using SramReadWithInfo/SramWriteWithInfo; added metadata muxing for write arbitration
MemDomain.scala Removed ToPhysicalLine instantiations; simplified connections by wiring translator directly to scratchpad
MemController.scala Removed redundant self-import of MemController
README.md Updated documentation to reflect unified architecture; expanded module descriptions and interface specifications

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val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W))
}

class AccMonitorReadIO(n: Int, w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle{
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Missing space before opening brace. Should be 'Bundle {' instead of 'Bundle{'.

Suggested change
class AccMonitorReadIO(n: Int, w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle{
class AccMonitorReadIO(n: Int, w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle {

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}


class AccReadRouter(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module {
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Missing space after closing parenthesis before 'extends'. Should be ') extends' instead of ')extends'.

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}


class AccMonitor(n: Int, w: Int, aligned_to: Int, single_ported: Boolean) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module {
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Missing space after closing parenthesis before 'extends'. Should be ') extends' instead of ')extends'.

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Comment on lines +57 to +60
valid_reg := io.write_in.io.req.valid
addr_reg := io.write_in.io.req.bits.addr
data_reg := io.write_in.io.req.bits.data
mask_reg := io.write_in.io.req.bits.mask
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The pipeline register valid_reg is updated based on io.write_in.io.req.valid without checking if the transaction actually fires (i.e., both valid and ready are true). This should be valid_reg := io.write_in.io.req.fire to ensure the pipeline only advances when the request is accepted. Similarly, addr_reg, data_reg, and mask_reg should also be conditionally updated using when(io.write_in.io.req.fire).

Suggested change
valid_reg := io.write_in.io.req.valid
addr_reg := io.write_in.io.req.bits.addr
data_reg := io.write_in.io.req.bits.data
mask_reg := io.write_in.io.req.bits.mask
valid_reg := io.write_in.io.req.fire
when (io.write_in.io.req.fire) {
addr_reg := io.write_in.io.req.bits.addr
data_reg := io.write_in.io.req.bits.data
mask_reg := io.write_in.io.req.bits.mask
}

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Comment on lines +109 to +111
bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, main_isacc_sel)
bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid)
bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid)
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Inconsistent alignment in assignment statements. The spacing between field names and assignment operators should be uniform across lines 109-111 for better readability.

Suggested change
bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, main_isacc_sel)
bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid)
bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid)
bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, main_isacc_sel)
bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid)
bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid)

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import framework.memdomain.mem.{SramReadIO, SramWriteIO}
import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo}

class AccMonitorWriteIO(n: Int, w: Int, mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters)extends Bundle {
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Missing space after closing parenthesis before 'extends'. Should be ') extends' instead of ')extends'.

Suggested change
class AccMonitorWriteIO(n: Int, w: Int, mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters)extends Bundle {
class AccMonitorWriteIO(n: Int, w: Int, mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle {

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2 participants