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There are many chanegs to the OpenSIL design since Genoa. Some MPIO macros are even missing. Ensure evrything is initialized correctly and the OpneSIL builds. Upstream-Status: Pending Change-Id: I388fe0171c07bd423e1344fbe380187052895b35 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
…ntry/exit Change-Id: I86ebec73c281625eca7376992f3c8d6492eea183 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6d6d3b73fc840f3cc366c5d221df8c18f27bd425 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
On Phoenix AM5 platform a similar problem to Turin platform occured. If coreboto set a different ECAM_MMCONF_BASE_ADDRESS than PSP in ABL, the PCI access did not work. Thankfully the SMN base address and DF registers are the same for Phoenix and Turin, which suggests that the synchronization of PCI MMCONF address in DF may be in common code. TEST=Set an arbitrary PCI MMCONF in coreboot above TOM address and see bootblock is still giving signs of life on serial console on MSI PRO B850-P. Change-Id: Ibf39bdba4dfd1c461bcd835f07118cf6b0fd1bb6 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
If the xHCI MMIO does not respond it may return all FFs. This causes the code to loop through entire xHCI MMIO resource region slowing down the boot process. Also fix iterating over the capabilities. The next capability pointer also denotes the number of words to the next capability, so the current pointer has to be moved by a next capability pointer shifted left by two bits. See xHCI specification for the next capability pointer field description. Change-Id: I777736d3f4b8493b2d2c3aca7882961eb95d7a77 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifaa218ab8e1d799f7e053481175c7375c2cabc3d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Fix scope of serial redirection options and remove duplicates. Upstream-Status: Inappropriate [custom build options] Change-Id: I07379ecdd4f4752cf7eeaa5b3772369406383a34 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
IOMMU VF BARs are available only on server for now. Guard VF BAR init with new Kconfig option to avoid setting them in unsupported HW. Upstream-Status: Pending Change-Id: I365e5d472335d3b79aebf16f2df6a280b8bd87b0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
On newer platforms there is SPI_ADDR32_CTRL0 with SPI_ROM_ADDR_32BIT controllign whether the SPI controller takes 32bit flash address for SPI transactions or not. Upstream-Status: Pending Change-Id: Ia655469acea37ae6416ab00f49e64fcb3ba88d75 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The PSP_BASE_MSR register has to be programmed with the CPP MMIO base address. Add API to obtain the address, so that SoC code can program the MSR during CPU init if necessary. Upstream-Status: Pending Change-Id: I37bd5177d0d406c0ab6588438ab1d39c728bb4ad Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Program PSP_BASE_MSR on BSP if not yet programmed and if CCP MMIO has been allocated. Upstream-Status: Pending Change-Id: I2f5d9e2f47244b6bb71a472b145969f9b0d4b40a Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Report the root bridge information to EDK2 to avoid problems with root bridge apertures reporting. Similar problem occured on Turin system. Upstream-Status: Pending Change-Id: I5c0e01033b8afdefc9944690deac368dccaac7e8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
IVRS should report DMA-capable non-PCI devices using ACPI HID and UIDs. Send the IVRS table to PSP for future DRTM support. Change-Id: I4412bc529e2cdff47b460e08c86fd3bce42c0a2b Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add necessary PSP commands so that the PSP Boot Done message does not halt the platform. Upstream-Status: Pending Change-Id: If73a2b710d2b0cb3f34dd27e3fb952dc8a815106 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Synchronize all ACPI I/O ports with what coreboot expects it to be. Pass additional coreboot configurtion to openSIL to match the behavior with Kconfig. Upstream-Status: Pending Change-Id: I262406ce33ba842f862f60146841155a1afaf41c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add IRQ routing and GPIO configuration. Limit the coreboot to 16MB, because flashing whole 32MB is time consuming. Change-Id: I1255076f6d55a5e96a3d43217e2fc4f442d267e8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
For some reason the call to enable IOAPIC decoding was not present. Almost all AMD SoCs do that, so add it for Phoenix too. Upstream-Status: Pending Change-Id: Ia45c344994dd4cadb9ce46ad3fec97a2aff4074d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Inappropriate [custom config] Change-Id: I60362b14985fd4cb6ee3b295c5b777e3db406951 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending Change-Id: I14824f465a5ec138a1f3b0141774c9a84972845c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Do not poll for ROM Armor enforcement if we didn't enable RON Armor in the build at all. It saves precious time spent in SMM. Upstream-Status: Pending Change-Id: Idafdb7433ddfa8ff22b80818b4772f801e43b0a3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
…ties Follow Turin's example and set bus master on PSP. Update HSTI at the end of coreboot so that OS PSP driver see all capabilities. Upstream-Status: Pending Change-Id: I78358b97b743798e0d99a8952f7de4788b8414a0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add SD controller to the device list. Despite it is no longer available in silicon according to PPR, it may appear on PCI bus if not disabled by silicon initialization module. Upstream-Status: Pending Change-Id: Ia99cdbc355d3714997b039370e049496a5c7acb1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending Change-Id: Ib130ea05deb3a85a62641fbe89369660a9def256 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The PCI MMCONF can not be moved and has to be in sync with APCB. Assign I/O address for ACPI so that the resource allocator does not complain on resource that didn't fit. Upstream-Status: Pending Change-Id: I66d4700d56477e06973ba46ae05d0232e5536608 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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