RTL Engineer in progress
| SystemVerilog | Verilog | VLSI
| Turning logic into hardware
| Learning verification
| Building designs & testbenches
-
Design Verification Trainee at Silicon Craft VLSI
- Chennai
Pinned Loading
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.