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Functional Simulator for subset of RISCV Processor

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This is the final project of CS204 - Computer Architecture Course. The project involves building a RISCV-32 Simulator. All the code is written in C++.

Group Members

1. Hardik Aggarwal
2. Komalpreet Singh
3. Ritesh Mohan Patil
4. Edgar Aditya Thorpe

The project is divided into three phases:

Phase 1:

• Implemented single cycle design with various instructions of RISC V

Phase 2:

• Implemented five-stage pipeline with stages IF, DE, EX, MA, WB.
• Implemented data forwarding and data stalling to remove hazards
• Implemented branch prediction to reduce stalls

Phase 3:

• Implemented cache memory
• Implemented various cache replacement policies such as FIFO, LRU, LFU and Random