Cache alignement on H7

[3djc]

Is there an existing issue for this problem?

• I have searched the existing issues

What part of EdgeTX is the focus of this bug?

Transmitter firmware

Current Behavior

Some DCache line are aligned at 4byte isntead of 32

Expected Behavior

All Dcache line should be 32Byte alligned

Reference: https://community.st.com/t5/stm32-mcus-touchgfx-and-gui/different-cache-behavior-between-stm32h7-and-stm32f7/m-p/151165

Version

Any supporting H7

Transmitter

H7

[richardclli]

Not necessary that all buffers required 32 bytes (cache line size) alignment. This alignment requirement os only for DMA read and write buffers separation.

Please read the followings for details:
https://community.st.com/t5/stm32-mcus/dma-is-not-working-on-stm32h7-devices/ta-p/49498

So the best practice is to group DMA buffers into 2 DMA buffer areas (read and write areas), and ensure these 2 areas are 32 bytes aligned.