verilog-generator v0.2.8

What's New

• Adds the RTL-MD constraint catalog and carries MUST/REC RTL rules into prompts, static lint, and review evidence.
• Adds read-only workflow routing for spec-first generation, plan-seeded generation, existing-RTL assist, and evidence-first repair.
• Strengthens ADC/DAC family guidance with JESD, SPI, and mixed-signal use-case templates.
• Extends validation and verify-repair coverage for RTL-MD constraints, diagnosis routing, and workflow reports.

Verification

• Imported from the sanitized v0.2.8 release package.
• Secret and forbidden-path scans passed before release.
• Python compile checks, CLI version check, and version metadata checks passed locally.