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Merged
merged 2 commits into from
Mar 13, 2024
Merged

LSE max wait patches #1

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7ed8236
LSE max wait patches for rusEFI
nmschulte Jan 7, 2023
12c805f
FOME-ize LSE max_wait patches
nmschulte Mar 13, 2024
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11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F0xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -68,23 +68,30 @@ static void hal_lld_backup_domain_init(void) {

/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif

#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F0xx/hal_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -376,6 +376,25 @@
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
Expand Down
11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F1xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,23 +66,30 @@ static void hal_lld_backup_domain_init(void) {

/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif /* STM32_LSE_ENABLED */

#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* Prescaler value loaded in registers.*/
rtc_lld_set_prescaler();
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F1xx/hal_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -177,6 +177,25 @@
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif
/** @} */

/*===========================================================================*/
Expand Down
11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F37x/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -65,23 +65,30 @@ static void hal_lld_backup_domain_init(void) {

/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif

#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F37x/hal_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -347,6 +347,25 @@
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
Expand Down
11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F3xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -65,23 +65,30 @@ static void hal_lld_backup_domain_init(void) {

/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif

#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F3xx/hal_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -387,6 +387,25 @@
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
Expand Down
11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F4xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -64,23 +64,30 @@ static void hal_lld_backup_domain_init(void) {
}

#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif

#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
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Original file line number Diff line number Diff line change
Expand Up @@ -620,6 +620,25 @@
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief USB/SDIO clock setting.
*/
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
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Original file line number Diff line number Diff line change
Expand Up @@ -402,6 +402,25 @@
#define STM32_LSE_ENABLED FALSE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief USB/SDIO clock setting.
*/
Expand Down
11 changes: 9 additions & 2 deletions os/hal/ports/STM32/STM32F7xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -64,23 +64,30 @@ static void hal_lld_backup_domain_init(void) {
}

#if STM32_LSE_ENABLED
int fomeLseCounter = 0;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
/* Waits until LSE is stable or times out. */
while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
&& (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
;
#endif

#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
#else
RCC->BDCR |= STM32_RTCSEL;
#endif

/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
Expand Down
19 changes: 19 additions & 0 deletions os/hal/ports/STM32/STM32F7xx/hal_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -541,6 +541,25 @@
#define STM32_LSE_ENABLED TRUE
#endif

/**
* @brief Number of times to busy-loop waiting for LSE clock source.
* @note The default value of 0 disables this behavior.
* @note See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX 0
#endif

/**
* @brief Fallback RTC clock source if stopped waiting for LSE clock source.
* @note If waiting for the LSE clock source times out due to
* FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
* fallback to another.
*/
#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
#define FOME_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSE
#endif

/**
* @brief USB/SDIO clock setting.
*/
Expand Down
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