This repository contains a collection of Verilog files used for the design of an SD (Secure Digital) card interface. These files are part of a development project aimed at creating or testing SD card functionalities for FPGA or ASIC implementations. Below is an overview of the key components within this project:
dev_sd_box.v: Top module that integrates the SD card interface components.sd_rbus_if.v: RingNet interface module for the top SD module. Incorporates FIFOs for clock domains transition