RV32I Single-Cycle RISC-V Core

Overview

This project implements a single-cycle RISC-V processor core supporting the RV32I base integer instruction set. The design is written in Verilog RTL and focuses on clarity, correctness, and timing efficiency, making it suitable for educational purposes, FPGA implementation, and timing analysis experiments.

A key design decision of this project is to support only RV32I, excluding extensions such as RV32M (multiply/divide) or floating-point units. This choice significantly improves maximum operating frequency (Fmax) and simplifies Static Timing Analysis (STA).

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Key Features

• RV32I base instruction set
• Single-cycle datapath
• Fully synchronous design
• Simple ALU (no MUL/DIV)
• Timing-friendly architecture
• Suitable for FPGA synthesis and STA

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Supported Instruction Set (RV32I)

Arithmetic & Logical

• ADD, SUB
• AND, OR, XOR
• SLL, SRL, SRA
• SLT, SLTU

Immediate Instructions

• ADDI, ANDI, ORI, XORI
• SLTI, SLTIU
• Shift-immediate instructions

Memory Access

• LW
• SW

Control Flow

• BEQ, BNE, BLT, BGE, BLTU, BGEU
• JAL, JALR

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Architecture

This is a single-cycle processor, meaning each instruction completes all stages within one clock cycle:

1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Execute (EX)
4. Memory Access (MEM)
5. Write Back (WB)

Because all stages execute in one cycle, the clock period must accommodate the slowest instruction path, making timing analysis critical.

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Datapath Overview

Typical critical path:

PC → Instruction Memory → Decode → Register File Read
   → ALU → Data Memory → Write Back

The absence of complex arithmetic units ensures that this path remains short and predictable, which directly improves Fmax.

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Why RV32I Only?

Timing Considerations

In a single-cycle design:

• All instructions share the same clock period
• The slowest instruction defines the clock frequency

Including extensions such as RV32M would introduce:

• Large combinational multipliers
• Deep logic trees
• Long carry propagation paths

This would drastically increase the critical path delay and reduce Fmax for all instructions.

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Static Timing Analysis (STA) Perspective

STA verifies that:

Tclk ≥ Tcq + Tcomb + Tsetup + Tskew

By restricting the ISA to RV32I:

• Tcomb is minimized
• Timing closure is easier
• Fewer timing violations occur

Result: Higher achievable clock frequency and cleaner STA reports.

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Design Files

File	Description
DatapathSingleCycle.v	Top-level single-cycle datapath
cla.v	Carry Look-Ahead adder used in ALU
Control.v	Instruction decode and control logic
ALU.v	RV32I-compliant ALU
RegFile.v	32×32 register file

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Synthesis and Timing

This core is suitable for:

• FPGA synthesis (Vivado / Quartus)
• RTL simulation
• Static Timing Analysis (STA)

Typical STA checks:

• Worst Negative Slack (WNS)
• Critical path identification
• Maximum clock frequency (Fmax)

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Limitations

• No RV32M (MUL/DIV)
• No floating-point support
• No caches or MMU

These limitations are intentional to preserve simplicity and timing efficiency.