RISC-V: Add RV32E / FPU support for GCC #140
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Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
n9wxu
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Sep 9, 2020
cobusve
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Description
Change vPortSetupTimerInterrupt in order to support 64bits RISC-V and modify mtime writing on 32bits RISC-V
Change portASM.s in order to support RV32E (16 registers instead of 32 registers on RV32I)
Change portASM.s in order to save/restore FPU registers on simple/double precision
Test Steps
tested on ARTY board with SIFIVE standard core E31, U54, S54 plus custom core with FPU (simple/double precision)
use "example-freertos-blinky" from freedom-e-sdk from SIFIVE (This change have not been yet committed into our public release, do not hesitate to communicate with me if you want to test it).
Related Issue
NONE
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