Fix delete key handling and assembler crashes#3
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## New instructions - **RV32A**: LR.W, SC.W, and all AMO variants (AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, AMOMAX, AMOMIN, AMOMAXU, AMOMINU) now route through the cache layer via `lr_w` / `sc_w` / `amo_w` on the `Bus` trait. LR/SC reservations are tracked per-hart inside `CacheController` (and per-hart in the CPU registers as a fallback for bypass mode). Any store to a reserved word cancels the reservation. - **FENCE**: forwards to `Bus::fence()` (was a no-op). - **FENCE.I**: implemented as `Bus::fence_i()`, invalidates the I-cache so self-modifying code picks up freshly written instructions. - Instruction panel type badges extended: `[A]` (atomic) and `[F]` (float). ## Cache coherence bug fixes (multi-level hierarchy) Four bugs that caused silent data corruption when L1 D-cache + L2 are both enabled (program crash at PC=0x00000000 with rust-to-raven.elf): 1. **Blanket L2 invalidation after write-back stores removed.** `dcache_store_bytes` was invalidating L2 after every store. On a write-allocate miss this sequence ran: fetch L2 → evict dirty D-cache line → writeback dirty data to L2 → then invalidate that same L2 line. Data ended up in neither cache level nor RAM (silent loss, corrupted stack return addresses → PC=0). 2. **Write-through stores now correctly invalidate L2.** Write-through keeps D-cache lines clean, so evictions never writeback to L2. After a write-through store, the L2 copy is stale and must be dropped so future misses re-read the updated value from RAM. 3. **`sync_to_ram` writeback order fixed.** Was: D-cache first, then L2. Now: L2 (reversed outer levels) first, then D-cache. D-cache is always authoritative; writing L2 last would overwrite correct D-cache data with stale L2 data in RAM. 4. **`flush_all` writeback order fixed** (same root cause as #3). Called when the user toggles the cache off; same reversal applied. ## Pipeline improvements - Per-FU (ALU, MUL, DIV, FPU, LSU, SYS) stall counters and configurable functional-unit counts. - Branch predictor extended: not-taken (default), always-taken, BTFNT, and 2-bit dynamic. - Per-hazard stall tag breakdown in the pipeline footer. - `.pcfg` config format updated: per-bypass-path flags replace single `forwarding` boolean; `fu.*` counts added. - Speculative Gantt: in-flight speculative instructions shown with distinct styling; flushed instructions marked. ## rust-to-raven - `raven_api` restructured: `hart.rs` moved to `hardware_thread/`, `atomic/` module added with `Arc`, `AtomicBool`, `AtomicU32`, etc. backed by LR.W/SC.W so they actually work on the simulator. - `main.rs` updated to use `HartTask` with a closure-based API.
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