Basic_Verilog_Projects

Here I have Designed Some of the Minor Circuits using Verilog During my Engineering 3rd year.
- contains : Combinational and Sequential Circuits
- Feel free to use them for your reference and modify or optimize if you get any idea on them further.
- Don't forget to share your feedback.
Thank You...

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
8x3_enco.v		8x3_enco.v
ALU_2bit.v		ALU_2bit.v
Basic_Gates.v		Basic_Gates.v
DFF.v		DFF.v
FA_task.v		FA_task.v
LICENSE		LICENSE
README.md		README.md
adder_2bit.v		adder_2bit.v
bus_arbiter.v		bus_arbiter.v
comp_1bit.v		comp_1bit.v
counter_3bit.v		counter_3bit.v
dec_3x8.v		dec_3x8.v
fa.v		fa.v
gray_binary.v		gray_binary.v
ha_df.v		ha_df.v
jk_dff.v		jk_dff.v
mult_3bit.v		mult_3bit.v
multipler.v		multipler.v
mux_4x1.v		mux_4x1.v
mux_8x1.v		mux_8x1.v
pipo.v		pipo.v
ripple_adder.v		ripple_adder.v
sd1011_moore.v		sd1011_moore.v
siso.v		siso.v
subtractor_2bit.v		subtractor_2bit.v

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