This repository contains the source code and RTL for RST, a hardware memory compression algorithm that enables random access to individual 64B compressed blocks using a 128B-per-page decompression dictionary.
Paper: "Random-Access Hardware Sequence Compression," ISCA 2026.
Authors: Nolan Chu, Yoon Lee, Gagandeep Panwar, Xun Jian — Virginia Tech & AMD Research.
The complete artifact (source, RTL, memory dumps, QEMU VM image, and synthesis evidence) is available on Zenodo:
https://doi.org/10.5281/zenodo.19449274
See the Zenodo archive's README.md for setup and experiment instructions.
BSD 3-Clause Clear. See LICENSE for details.