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BNDMOV
BNDMOV — Move Bounds
| Opcode/ Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
| 66 0F 1A /r BNDMOV bnd1, bnd2/m64 | RM | NE/V | MPX | Move lower and upper bound from bnd2/m64 to bound register bnd1. |
| 66 0F 1A /r BNDMOV bnd1, bnd2/m128 | RM | V/NE | MPX | Move lower and upper bound from bnd2/m128 to bound register bnd1. |
| 66 0F 1B /r BNDMOV bnd1/m64, bnd2 | MR | NE/V | MPX | Move lower and upper bound from bnd2 to bnd1/m64. |
| 66 0F 1B /r BNDMOV bnd1/m128, bnd2 | MR | V/NE | MPX | Move lower and upper bound from bnd2 to bound register bnd1/m128. |
| Op/En | Operand 1 | Operand 2 | Operand 3 |
| RM | ModRM:reg (w) | ModRM:r/m (r) | NA |
| MR | ModRM:r/m (w) | ModRM:reg (r) | NA |
BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.
| Upper Bound (UB) Lower Bound (LB) BNDMOV to memory in 64-bit mode 16 8 0 Byte offset Upper Bound (UB) Lower Bound (LB) BNDMOV to memory in 32-bit mode 16 8 4 0 Byte offset | ||||||||||||||
| Upper Bound (UB) | Lower Bound (LB) | |||||||||||||
| Upper Bound (UB) | Lower Bound (LB) | BNDMOV to memory in 32-bit mode 4 0 Byte offset | ||||||||||||
Figure 3-5. Memory Layout of BNDMOV to/from Memory
This instruction does not change flags.
DEST.LB ← SRC.LB;
DEST.UB ← SRC.UB; IF 64-bit mode THEN
DEST.LB ← LOAD_QWORD(SRC);
DEST.UB ← LOAD_QWORD(SRC+8);
ELSE
DEST.LB ← LOAD_DWORD_ZERO_EXT(SRC);
DEST.UB ← LOAD_DWORD_ZERO_EXT(SRC+4);
FI;IF 64-bit mode THEN
DEST[63:0] ← SRC.LB;
DEST[127:64] ← SRC.UB;
ELSE
DEST[31:0] ← SRC.LB;
DEST[63:32] ← SRC.UB;
FI;BNDMOV
void * _bnd_copy_ptr_bounds(const void *q, const void *r)None
#UD If the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 67H prefix is not used and CS.D=0. If 67H prefix is used and CS.D=1.
#SS(0) If the memory operand effective address is outside the SS segment limit.
#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the destination operand points to a non-writable segment If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code) If a page fault occurs.
#UD If the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 16-bit addressing is used.
#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If the memory operand effective address is outside the SS segment limit.
#UD If the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 16-bit addressing is used.
#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If the memory operand effective address is outside the SS segment limit.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code) If a page fault occurs.
Same exceptions as in protected mode.
#UD If the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0) If the memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code) If a page fault occurs.
Source: Intel® Architecture Software Developer's Manual (May 2018)
Generated: 5-6-2018