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FXCH
FXCH — Exchange Register Contents
Opcode | Instruction | 64-Bit Mode | Compat/ Leg Mode | Description |
D9 C8+i | FXCH ST(i) | Valid | Valid | Exchange the contents of ST(0) and ST(i). |
D9 C9 | FXCH | Valid | Valid | Exchange the contents of ST(0) and ST(1). |
Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.
This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack:
FXCH ST(3); FSQRT; FXCH ST(3); This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
IF (Number-of-operands) is 1
THEN
temp ← ST(0);
ST(0) ← SRC;
SRC ← temp;
ELSE
temp ← ST(0);
ST(0) ← ST(1);
ST(1) ← temp;
FI;
C1 Set to 0. C0, C2, C3 Undefined.
#IS Stack underflow occurred.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF If there is a pending x87 FPU exception.
#UD If the LOCK prefix is used.
Same exceptions as in protected mode.
Same exceptions as in protected mode.
Same exceptions as in protected mode.
Same exceptions as in protected mode.
Source: Intel® Architecture Software Developer's Manual (May 2018)
Generated: 5-6-2018