nightly-20260704

Added

• C1 completed for everything that pays without register residency: MOVZX/MOVSX byte loads under $CPU 80386 (a BYTE/SBYTE cell read widens in one instruction instead of MOV + XOR AH / CBW) joining the already-shipped constant-divisor 32-bit IDIV/DIV, inline IMUL EAX for LONG multiply, QUAD bitwise/SHLD-SHRD shifts, 32-bit shift/rotate collapse, DWORD block primitives and branchless SETcc relational results * the two remaining checklist lines are recorded where they belong: LONG add/sub stay the two-op ADD/ADC pair because a scratch-staged EAX form is SLOWER without register residency, and scaled-LEA addressing needs the 32-bit ModRM/SIB encoder - both are the 386 register-allocation substrate tracked under O5's 386 tier + DOSBox run: BYTE/SBYTE widening loads verified output-identical optimized vs unoptimized under $CPU 80386 $OPTIMIZE SPEED (6ce640a)