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Introduce HDL21 Synthesis Tools #59
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So for simplicity, I've decided to just borrow lessons from the HDL21 core to implement what is useful, generally we have a @psl.pcircuit decorator which produces named instances of PCircuit and @psl.module decorator which is a big port handling object ModuleContext in psl/context.py which effectively keeps track of multiple @psl.pcircuit instantiations so that they be connected with the modes with the ConnectionType class in p_kit/psl/port.py: Directly as in the Onizawa's Framework [1] There are also two synthesis modes |
gcattan
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@ThomasPluckMU thank you for your hard word.
Please find below a few comments.
…Circuit, added heatmap, examples, tidied docs, deleted .core, formatted with black .
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Okay, I think this addresses most of the points that came up in review. Let me know if anything else comes up that's of interest to you. I could try to take a stab at #62 unless you want to leave that for the next PR? |
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Sure. We can keep #62 for another PR :) I see the Ci is failing: Do you also want to keep the util module at the end? |
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Works on my computer! (Will patch this tomorrow) |
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Thank you for your work @ThomasPluckMU !
Looking forward to your next contribution

HDL21 is a Python-based HDL which makes Verilog style module definitions and routing simple and intuitive where it is then boiled down to a protobuf interchange format that can be translated into any desired format, eg. SPICE netlists, GDS Layouts, etc.
My main interest in p-computing is that I need to build large PSL circuits fast, and it'd be good to have it as a part of one-stop shop where folks could get the circuit of their hearts desire and run whatever algorithms they want against it.
To this end, this PR will go out of draft once it has the following deliverables: