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3. General Workflow Guide

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RomiSolMolina edited this page Jun 9, 2026 · 1 revision

General Workflow

Throughout the course, students will follow a complete end-to-end workflow that transforms a trained neural network model into a hardware accelerator running on the AMD AUP-ZU3 platform. Although each case study focuses on a specific architecture (MLP, CNN, RNN), the overall process remains consistent. This section provides a high-level guide to the major stages and the corresponding Jupyter notebooks or tools used in each step.

1. Model Training

The workflow begins with training the neural network using the provided Jupyter notebooks.

This stage includes:

  • Dataset loading and preprocessing.

  • Model definition and training.

  • Modle performance evaluation.

  • Saving outputs in a standardized format (model.h5).

These files serve as the inputs for later compression and hardware translation.

2. Model Compression

Next, optional compression techniques are applied to reduce the computational cost and memory footprint of the model:

  • Quantization (lower-precision weights and activations).

  • Pruning (removal of redundant parameters).

  • Knowledge Distillation (training a compact student network).

The corresponding notebook demonstrates how each technique affects accuracy and hardware suitability.

3. Hardware Generation with hls4ml

The compressed (or uncompressed) model is then converted into synthesizable hardware using hls4ml.

This stage covers:

  • Creating an hls4ml configuration from model.h5.

  • Adjusting reuse factors and precision settings.

  • Generating C++ project files compatible with Vitis HLS.

  • Running C-synthesis, and exporting the IP core.

The notebook guides the process and produces an IP block ready for integration in Vivado.

4. Vivado Block Design

In this step, a reusable block design is created, that integrates:

  • The hls4ml-generated IP core.

  • AXI DMA for data movement.

  • Clocking and reset infrastructure.

  • Connections to the Zynq processing system.

Only the accelerator IP changes between case studies; the rest of the design remains common.

A reference Vivado project and build script are provided to streamline this process.

5. Deployment on PYNQ

Once the bitstream and hardware handoff files are generated, the next step is to deploy the design on the AUP-ZU3 board using the PYNQ environment.

This involves:

  • Connecting to the board via JupyterLab or SSH.

  • Uploading the .xsa file and notebook files.

  • Loading the overlay.

  • Initializing the AXI DMA engine.

  • Running inference tests.

The provided PYNQ template ensures a consistent evaluation workflow across all experiments.

This work was supported in part by the AMD University Program

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