1. Introduction

DLX (Deluxe)

The DLX processor is a 32-bit RISC architecture designed by John L. Hennessy and David A. Patterson in 1994. This CPU is used as of today to teach students about architecture and assembly language because of simple design compared to modern architectures. It has 32 General purpose registers, 32 Floating point register (paired for 64-bit doubles)

History

In the Stanford MIPS architecture one of the methods used to gain performance was to force all instructions to complete in one clock cycle. This forced compilers to insert no-ops in cases where the instruction would definitely take longer than one clock cycle. Thus input and output activities (like memory accesses) specifically forced this behaviour, leading to artificial program bloat. In general MIPS programs were forced to have a lot of wasteful NOP instructions, a behaviour that was an unintended consequence. The DLX architecture does not force single clock cycle execution, and is therefore immune to this problem.

In the DLX design a more modern approach to handling long instructions was used: data-forwarding and instruction reordering. In this case the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they can complete. Externally this design behaviour makes it appear as if execution had occurred linearly.

Source: Wikipedia

Design

DLX instructions can be broken down into three types, R-type, I-type and J-type. R-type instructions are operation between registers so the instruction references 3 registers. I-type are immediate operations, the instruction contains on itself one of the operands while the other is stored in the register referenced. The J-type instructions are jumps that contains an absolute memory address.

The instruction Opcode lives in the first 6 bits for up to 64 instructions, for each register reference 5 bits are used. This means that

• R-type instruction have 11 bits left that are used to specify a offset or an extended instruction.
• Using these extended fields allow the DLX to have extensions created or more than 64 instructions as long as they only use registers.
• I-type instructions have a limit of 16-bits for immediate numbers or addresses in branch instructions.
• J-type Has 26-bits addressable for jumps

The DLX architecture is segmented this means that the execution of each instruction is divided in several stages, the DLX pipeline is as follows:

Instruction fetch unit (IF)

In this stage the Program Counter (PC) is loaded into the Instruction Memory Adress Register (IMAR) Wich is connected to the memory bus and the instruction is placed into the Instruction Register. PC is incremented by 4.

Instruction decode unit (ID)

The decoding stage include reading the opcode from the instruction fetched and loading the values into the operand registers A and B. It also calculates if any of the data needed is being calculated and stalls the CPU and wait for the data to be ready either in the register or in a point where it can be forwarded from other units.

Execution unit (EX)

It's only job is to load the data from register A and B in the appropriate unit, be it the ALU or any of the FPU available. Memory addresses for jumps, load/stores is calculated here.

Memory access unit (MEM)

This stage only is used if the instruction is a load or a store and loads the address calculated in the previous stage and places the Save Data Register (SDR) into the memory address in the Data Memory Address Register (DMAR) or loads the address into Load Data Register (LDR).

Writeback unit (WB)

Finally the last step is to write any previously calculated data or load to the specified register.

WinDLX

WinDLX is the reference emulator for the DLX architecture it dates back to Windows 3.1 era an hasn't been updated since. WinDLX is used as based and the reference behaviour for this project , this emulator should produce identical results, but these are the differences:

• THUMDER will produce an extra clock cycle due to how the trap #0 is handled.
• Similar to the previous case, it will count an extra instruction decode.
• Trap are not implemented, so no trap stall is accounted for. This will give a minimum of 3 stalls less than WinDLX.
• The IR register is not shown on the register list due to it being a segmented processor, there is one IR per stage.
• Instructions and OpCodes are completely different as there is no way around this. WinDLX is closed source and there is no documentation left of what codes were used to assemble the instructions. And the DLX architectures has no definitive OpCodes, not even in the book it was defined includes a table for those.

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