Project created for ELEC 374 Digital Systems Engineering course.

The purpose of this project is to design, simulate, implement, and verify a simple RISC Computer (Mini SRC), consisting of a simple RISC processor, memory, and I/O. The project consists of the design and Functional Simulation of the rest of the Mini SRC datapath. This includes the circuits associated with the “Select and Encode” logic, “Memory Subsystem”, “CON FF” logic, and “Input/Output” ports, as well as load/store instructions, branch and jump instructions, and immediate instructions.

This projected was created in Verilog using Quartus, and the functional simulations were run using Altera ModelSim.# Simple-RISC-Computer