COMPANY : CODTECH IT SOLUTIONS
NAME : REDDY HEMANTH KUMAR
INTERN ID : CTIS3666
DOMAIN : VLSI
DURATION : 6 MONTHS
MENTOR : NEELA SANTHOSH KUMAR
DESCRIPTION :
Digital FIR Filter Design and Simulation using Verilog
This repository contains the complete implementation of a Digital Finite Impulse Response (FIR) filter designed and simulated using Verilog HDL. The project demonstrates the practical design, modeling, and verification of a basic digital signal processing system in hardware description language.
The FIR filter is implemented as a 4-tap synchronous digital filter that performs convolution between input data samples and predefined filter coefficients. The design follows a fully synchronous architecture using shift registers and multiplier-adder operations. The filter accepts 8-bit signed input samples and generates 16-bit signed output results based on the FIR equation:
y[n] = h[0]x[n] + h[1]x[n–1] + h[2]x[n–2] + h[3]x[n–3]
The repository includes synthesizable Verilog source code for the FIR filter module along with a comprehensive testbench to verify its functionality. The testbench applies a sequence of input samples to the filter and monitors the corresponding output responses in simulation.
Simulation was carried out using industry-standard HDL simulation tools such as ModelSim / Vivado. Waveforms and console outputs were analyzed to confirm correct filter behavior, timing accuracy, and functional correctness. The project validates important digital design concepts such as pipelining, sequential logic, and real-time signal processing.
Repository Contents
fir_filter.v – Verilog module implementing the FIR filter
fir_tb.v – Testbench for functional verification
Simulation Results – Waveform screenshots and console output
Project Report – Explanation of design, simulation, and analysis
Features
Fully synchronous FIR filter architecture
Fixed coefficient implementation
Real-time sample processing
Behavioral simulation and verification
Simple, modular, and synthesizable design
Performance Analysis
Latency: 4 clock cycles (equal to number of taps)
Throughput: 1 output sample per clock cycle
Hardware usage: 4 multipliers, 3 adders, 3 registers
Stable and linear phase response (typical FIR advantage)
Tools Used
Verilog HDL
ModelSim / Vivado Simulator
MATLAB (optional for reference analysis)
Applications
This project serves as an educational reference for digital signal processing, FPGA design, and hardware modeling. It can be extended to higher-order FIR filters, programmable coefficients, or real-time FPGA implementations.
How to Use
Clone the repository
Compile fir_filter.v and fir_tb.v in any Verilog simulator
Run simulation
Observe output waveform and console results
OUTPUT :
