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1. AXIPROTOCOL-THROUGH-FIFO AXIPROTOCOL-THROUGH-FIFO Public

   This Project aims to design the working of AMBA Bus Architechture, considering the AXI protocol. AXI protocol defined for high-frequency, high-bandwidth systems for data communication.

   Verilog 8 2

2. FIFO_-asynchronous FIFO_-asynchronous Public

   Forked from zhangkunming0216/FIFO_-asynchronous

   异步FIFO的内部实现

   Verilog

3. ARM ARM Public

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4. MIPS-SINGLE-CYCLE-PROCESSOR MIPS-SINGLE-CYCLE-PROCESSOR Public

   32-bit single cycle MIPS processor has been implemented with a set of instructions including the Arithmetic, Logical , Bitwise & conditional instructions

   Verilog

5. 5-Stage-Pipelined-MIPS-Processor 5-Stage-Pipelined-MIPS-Processor Public

   Verilog