I’m an Electrical & Computer Engineering student at the University of Washington focused on computer architecture, digital design, and hardware acceleration. I’m most interested in building serious, reproducible systems projects—especially where low-level design, performance, and clear technical documentation all matter.
My strongest work sits at the intersection of RTL design, pipelined processors, FPGA/HLS workflows, and benchmark-driven engineering. I like projects that go beyond “it works” and show how the system was built, tested, and improved.
- Digital systems and computer architecture projects
- RTL/SystemVerilog designs
- FPGA and HLS-based acceleration workflows
- Performance-focused projects with benchmarks, tests, and documentation
Built an unpipelined CPU from the gate level up and then redesigned it into a 5-stage pipelined version. Includes design artifacts, diagrams, testing, and benchmark/performance results.
- Computer architecture
- Hardware acceleration
- FPGA / HLS workflows
- Efficient compute systems
- Bridging low-level implementation with system-level performance
- LinkedIn: https://www.linkedin.com/in/leotxie/
- Academic Email: ltxie27@uw.edu
- Personal Email: leo.t.xie@gmail.com