ARM LDR — Alignment & Packed

Instruction	Size	Required alignment
LDR X0, [X1]	8 bytes (64-bit)	addr % 8 == 0
LDR W0, [X1]	4 bytes (32-bit)	addr % 4 == 0
LDRH W0, [X1]	2 bytes	addr % 2 == 0
LDRB W0, [X1]	1 byte	none

; packed: int at offset 1 (unaligned)
; compiler replaces one LDR with 4× LDRB + bit-shifts:
LDRB W0, [X1, #1]   ; byte 0 of int
LDRB W1, [X1, #2]   ; byte 1 of int
LDRB W2, [X1, #3]   ; byte 2 of int
LDRB W3, [X1, #4]   ; byte 3 of int

Architecture	Unaligned access result
ARMv8-A Linux (SCTLR.A=0)	hardware fixup, slower
Cortex-M0 / M0+	HardFault!
Cortex-M3 / M4 / M7	partial fixup (LDR ok, LDM/STM no)
x86	works, slightly slower

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