volatile

// Bad — compiler caches the read at -O2
uint32_t *reg = (uint32_t *)0x40011004;
while (*reg & 0x01 == 0);    // also a precedence bug!

// Correct
volatile uint32_t *reg = (volatile uint32_t *)0x40011004;
while ((*reg & 0x01) == 0);  // fresh load every iteration

Requirement	Why
volatile	compiler must not cache — every access = actual load/store
aligned address	LDR requires addr % sizeof(type) == 0
~MASK before |=	OR alone cannot clear bits already set to 1