GitHub - Mayan-Gobin/UART_VHDL: This repository contains a lab project from CEG3155 (Digital Systems II), where we developed every individual component needed to implement UART in Quartus II using VHDL programming.

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This repository contains a lab project from CEG3155 (Digital Systems II), where we developed every individual component needed to implement UART in Quartus II using VHDL programming.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation		simulation
AddressDecoder.vhd		AddressDecoder.vhd
AddressDecoder.vhd.bak		AddressDecoder.vhd.bak
AddressDecoder.vwf		AddressDecoder.vwf
InterruptGenerator.vhd		InterruptGenerator.vhd
InterruptGenerator.vhd.bak		InterruptGenerator.vhd.bak
InterruptGenerator.vwf		InterruptGenerator.vwf
UART.qpf		UART.qpf
UART.qsf		UART.qsf
UART.qws		UART.qws
UART_Loop.bdf		UART_Loop.bdf
baudRateGen.bsf		baudRateGen.bsf
baudRateGen.vhd		baudRateGen.vhd
baudRateGen.vhd.bak		baudRateGen.vhd.bak
counter.vwf		counter.vwf
counter.vwf.temp		counter.vwf.temp
counter_6bit.vhd		counter_6bit.vhd
counter_8bit.vhd		counter_8bit.vhd
dFF.vwf		dFF.vwf
d_FF.vhd		d_FF.vhd
eightBitShiftRegister_R.bsf		eightBitShiftRegister_R.bsf
eightBit_eightToThreeMux.bsf		eightBit_eightToThreeMux.bsf
equality_Comparator_6bit.vhd		equality_Comparator_6bit.vhd
equality_Comparator_8bit.vhd		equality_Comparator_8bit.vhd
mux2to1_6bit.vhd		mux2to1_6bit.vhd
mux2to1_8b.vhd		mux2to1_8b.vhd
mux2to1_8bit.vhd		mux2to1_8bit.vhd
mux4to1_8b.vhd		mux4to1_8b.vhd
mux8to1_1bit.vhd		mux8to1_1bit.vhd
mux8to1_8b.vhd		mux8to1_8b.vhd
muxFourToTwo.bsf		muxFourToTwo.bsf
stateRegister.bsf		stateRegister.bsf
tdr.bsf		tdr.bsf
tdr.vhd		tdr.vhd
tdr.vhd.bak		tdr.vhd.bak
threeBitCounter.bsf		threeBitCounter.bsf
threeBitCounter.vhd		threeBitCounter.vhd
threeBitCounter.vhd.bak		threeBitCounter.vhd.bak
transmitter.bdf		transmitter.bdf
transmitter.bsf		transmitter.bsf
transmitterController.bsf		transmitterController.bsf
transmitterController.vhd		transmitterController.vhd
transmitterController.vhd.bak		transmitterController.vhd.bak
transmitterController.vwf		transmitterController.vwf
transmitterController.vwf.temp		transmitterController.vwf.temp
tsr.bsf		tsr.bsf
tsr.vhd		tsr.vhd
tsr.vhd.bak		tsr.vhd.bak
tsr.vwf		tsr.vwf
tsr.vwf.temp		tsr.vwf.temp
uart_FSM.vwf		uart_FSM.vwf
uart_FSM.vwf.temp		uart_FSM.vwf.temp
uart_fsm.bsf		uart_fsm.bsf
uart_fsm.vhd		uart_fsm.vhd
uart_fsm.vhd.bak		uart_fsm.vhd.bak

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This repository contains a lab project from CEG3155 (Digital Systems II), where we developed every individual component needed to implement UART in Quartus II using VHDL programming.