Cache Simulator in C

This project implements a simple cache simulator in C and uses trace-driven simulation to study cache performance under different configurations.

The simulator processes memory access traces and reports cache hit rates while varying key design choices such as block size and associativity. It also applies an LRU-style replacement strategy when needed.

Features

• Simulates cache behavior using memory access traces
• Tests the effect of different block sizes on cache hit rate
• Tests the effect of different associativity levels on cache hit rate
• Uses a simplified trace file for testing and demonstration
• Reports results for each experiment in a clear format

Files

• main.c – main source file for the cache simulator
• trace_simplified.txt – simplified trace file used as input
• results/experiment-output.txt – recorded experiment results
• results/output-screenshot.png – sample console output

How to Compile and Run

Compile the program with a C compiler, then run the executable.

Example with GCC:

gcc -o cache-simulator main.c
./cache-simulator